MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 281

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

register may be written by the mttbl or the mttbu instructions, see
—
Refer to
—
6.2.2.4.3
Two reference registers (TBREF0 and TBREF1) are associated with the lower part of the time base (TBL).
Each is a 32-bit read/write register. Upon a match between the contents of TBL and the reference register,
a maskable interrupt is generated.
Freescale Semiconductor
OEA.”
OEA” for more information on reading and writing the TBU and TBL registers.
PORESET
Reset
Reset
PORESET
Field
Field
Addr
Addr
Field
Section 3.8, “VEA Register Set — Time Base
Addr
Field
Addr
MSB
MSB
0
0
MSB
Time Base Reference Registers (TBREF0 and TBREF1)
MSB
0
0
Figure 6-32. Time Base Reference Register 0 (TBREF0)
Figure 6-33. Time Base Reference Register 1 (TBREF1)
MPC561/MPC563 Reference Manual, Rev. 1.2
TBU
Figure 6-30. Time Base (Reading) (TB)
TBU
Figure 6-31. Time Base (Writing) (TB)
SPR 269, SPR 268
SPR 285, SPR 284
Unaffected
0x2F C204
0x2F C208
Unaffected
TBREF0
TBREF1
Unaffected
Unaffected
(TB)’ and
31 32
31 32
Section 3.9.4, “Time Base Facility (TB)
Section 3.9.4, “Time Base Facility (TB)
System Configuration and Protection
TBL
TBL
LSB
LSB
63
31
LSB
LSB
31
63
6-41