MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 287

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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6.2.2.5.2
Freescale Semiconductor
1
If the device is configured NOT in full bus mode (i.e., SIUMCR[SC]=0b01, 0x10, or 0b11), the GPIO pins will be in input
Reset
Reset
mode and this register will reflect the state of the pins.
16:23
24:31
Field
Field
Addr
Bits
8:15
0:7
MSB
16
0
SGPIOA[8:15] SIU general-purpose I/O Group A[8:15]. This 8-bit register controls the data of the
SGPIOC[0:7] SIU general-purpose I/O Group C[0:7]. This 8-bit register controls the data of the
SGPIO Data Register 2 (SGPIODT2)
SGPIOA
SGPIOA
[16:23]
[24:31]
Name
17
1
18
2
general-purpose I/O pins SGPIOC[0:7]. The direction of SGPIOC[0:7] is controlled by 8
dedicated direction control signals SDDRC[0:7] in the SGPIO control register. Each pin in
this group can be configured separately as general-purpose input or output.
general-purpose I/O pins SGPIOA[8:15]. The GDDR3 bit in the SGPIO control register
configures these pins as a group as general-purpose input or output.
SIU general-purpose I/O Group A[16:23]. This 8-bit register controls the data of the
general-purpose I/O pins SGPIOA[16:23]. The GDDR4 bit in the SGPIO control register
configures these pins as a group as general-purpose input or output.
SIU general-purpose I/O Group A[24:31]. This 8-bit register controls the data of the
general-purpose I/O pins SGPIOA[24:31]. The GDDR5 bit in the SGPIO control register
configures these pins as a group as general-purpose input or output.
SGPIOA[16:23]
SGPIOC[0:7]
19
3
Figure 6-42. SGPIO Data Register 2 (SGPIODT2)
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 6-24. SGPIODT2 Bit Descriptions
20
4
21
5
0000_0000_0000_0000
0000_0000_0000_0000
22
6
0x2F C028
23
7
24
Description
8
25
9
1
1
10
26
SGPIOA[24:31]
SGPIOA[8:15]
11
27
System Configuration and Protection
12
28
13
29
14
30
LSB
15
31
6-47

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