MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 29

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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23.1
23.1.1
23.1.1.1
23.1.1.2
23.1.1.3
23.1.2
23.1.3
23.1.4
23.1.4.1
23.1.4.2
23.1.4.3
23.1.4.4
23.1.4.5
23.1.5
23.2
23.2.1
23.2.1.1
23.2.1.2
23.2.1.3
23.2.1.4
23.2.1.5
23.2.1.6
23.2.2
23.2.2.1
23.2.3
23.2.3.1
23.3
23.3.1
23.3.1.1
23.3.1.2
23.3.1.3
23.3.1.4
23.3.1.5
23.3.1.6
23.4
23.4.1
23.4.2
23.4.3
Freescale Semiconductor
Paragraph
Number
Program Flow Tracking ................................................................................................ 23-1
Watchpoints and Breakpoints Support ......................................................................... 23-7
Development System Interface ................................................................................... 23-19
Development Port ....................................................................................................... 23-28
Program Trace Cycle ................................................................................................ 23-2
Program Trace when in Debug Mode ....................................................................... 23-4
Sequential Instructions Marked as Indirect Branch .................................................. 23-4
External Hardware .................................................................................................... 23-4
Instruction Fetch Show Cycle Control ...................................................................... 23-7
Internal Watchpoints and Breakpoints ...................................................................... 23-9
Instruction Support ................................................................................................. 23-14
Watchpoint Counters .............................................................................................. 23-19
Debug Mode Support .............................................................................................. 23-21
Development Port Pins ........................................................................................... 23-28
Development Serial Clock ...................................................................................... 23-29
Development Serial Data In .................................................................................... 23-29
Instruction Queue Status Pins — VF [0:2] ........................................................... 23-2
History Buffer Flushes Status Pins— VFLS [0:1] ............................................... 23-3
Queue Flush Information Special Case ................................................................ 23-4
Synchronizing the Trace Window to the CPU Internal Events ............................ 23-5
Detecting the Trace Window Start Address ......................................................... 23-6
Detecting the Assertion/Negation of VSYNC ...................................................... 23-6
Detecting the Trace Window End Address .......................................................... 23-6
Compress .............................................................................................................. 23-7
Restrictions ......................................................................................................... 23-11
Byte and Half-Word Working Modes ................................................................ 23-11
Examples ............................................................................................................. 23-12
Context Dependent Filter .................................................................................... 23-13
Ignore First Match .............................................................................................. 23-14
Generating Six Compare Types .......................................................................... 23-14
Load/Store Support ............................................................................................. 23-16
Trap Enable Programming .................................................................................. 23-19
Debug Mode Enable vs. Debug Mode Disable .................................................. 23-23
Entering Debug Mode ......................................................................................... 23-24
Check Stop State and Debug Mode .................................................................... 23-26
Saving Machine State upon Entering Debug Mode ........................................... 23-27
Running in Debug Mode .................................................................................... 23-27
Exiting Debug Mode ........................................................................................... 23-28
MPC561/MPC563 Reference Manual, Rev. 1.2
Development Support
Contents
Chapter 23
Title
Number
Page
xxix

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