MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 315

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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The clocks GCLK1_50 and GCLK2_50 frequency is:
Figure 8-7
8.5.2
CLKOUT has the same frequency as the general system clock (GCLK2_50). Unlike the main system clock
GCLK1/GCLK2 however, CLKOUT (and GCLK2_50) represents the external bus clock, and thus will be
one-half of the main system clock if the external bus is running at half speed (EBDF = 0b01). The
CLKOUT frequency (system frequency) defaults to VCO/2. CLKOUT can drive full, half, or quarter
strength; it can also be disabled. The drive strength is controlled in the system clock and reset-control
register (SCCR) by the COM[0:1] and CQDS bits. (See
(SCCR)”). Disabling or decreasing the strength of CLKOUT can reduce power consumption, noise, and
electromagnetic interference on the printed circuit board.
When the PLL is acquiring lock, the CLKOUT signal is disabled and remains in the low state (provided
that BUCS = 0).
Freescale Semiconductor
GCLK1
GCLK2
GCLK1_50
(EBDF = 00)
GCLK2_50
(EBDF = 00)
CLKOUT
(EBDF = 00)
GCLK1_50
(EBDF = 01)
GCLK2_50
(EBDF = 01)
CLKOUT
(EBDF = 01)
shows the timing of USIU clocks when DFNH = 1 or DFNL = 0.
Clock Out (CLKOUT)
Figure 8-7. Clocks Timing For DFNH = 1 (or DFNL = 0)
FREQ 50
MPC561/MPC563 Reference Manual, Rev. 1.2
=
------------------------------------------------------------------ -
(
2
DFNH
FREQsysmax
)or 2
(
DFNL
Section 8.11.1, “System Clock Control Register
+
1
)
x
--------------------------
EBDF
1
+
1
Clocks and Power Control
8-13

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