MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 316

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Clocks and Power Control
8.5.3
ENGCLK is an output clock with a 50% duty cycle. Its frequency defaults to VCO/128, which is 1/64 of
the main system frequency. ENGCLK frequency can be programmed to the main system frequency
divided by a factor from one to 64, as controlled by the ENGDIV[0:5] bits in the SCCR. ENGCLK can
drive full- or half-strength, or it can also be disabled (remaining in the high state). The drive strength is
controlled by the EECLK[0:1] bits in the SCCR. Disabling ENGCLK can reduce power consumption,
noise, and electromagnetic interference on the printed circuit board.
When the PLL is acquiring lock, the ENGCLK signal is disabled and remains in the low state (provided
that BUCS = 0).
8.6
For limp mode support, clock source switching is supported. If for any reason the clock source for the chip
is not functioning, the option is to switch the system clock to the backup clock ring oscillator, BUCLK.
This circuit consists of a loss-of-clock detector, which sets the LOCS status bit and LOCSS sticky bit in
the PLPRCR. If the LME bit in the SCCR is set, whenever LOCS is asserted, the clock logic switches the
system clock automatically to BUCLK and asserts hard reset to the chip. Switching the system clock to
BUCLK is also possible by software setting the STBUC bit in SCCR. Switching from limp mode to normal
system operation is accomplished by clearing STBUC and LOCSS bits. This operation also asserts hard
reset to the chip.
At HRESET assertion, if the PLL output clock is not valid, the BUCLK will be selected until software
clears LOCSS bit in SCCR. At HRESET assertion, if the PLL output clock is valid, the system will switch
to oscillator/external clock. If during HRESET the PLL loses lock or the clock frequency becomes slower
than the required value, the system will switch to the BUCLK. After HRESET negation the PLL lock
condition does not effect the system clock source selection.
If the LME bit is clear, the switch to the backup clock is disabled and assertion of STBUC bit is ignored.
If the chip is in limp mode, clearing the LME bit switches the system to normal operation and asserts hard
reset to the chip.
Figure 8-8
each state.
8-14
Clock Source Switching
describes the clock switching control logic.
Engineering Clock (ENGCLK)
The full strength ENGCLK setting (SCCR[EECLK]=0b01) selects a 5-V
driver while the half-strength selection (SCCR[EECLK]=0b00) is a 2.6-V
driver.
Skew elimination between CLKOUT and ENGCLK is not guaranteed.
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
NOTE
Table 8-3
summarizes the status and control for
Freescale Semiconductor