MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 354

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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External Bus Interface
9.5.2.3
The general case of single beat transfers assumes that the external memory has a 32-bit port size. The
MPC561/MPC563 provides an effective mechanism for interfacing with 16-bit and 8-bit port size
memories, allowing transfers to these devices when they are controlled by the internal memory controller.
In this case, the MPC561/MPC563 attempts to initiate a transfer as in the normal case. If the bus interface
receives a small port size (16 or 8 bits) indication before the transfer acknowledge to the first beat (through
the internal memory controller), the MCU initiates successive transactions until the completion of the data
transfer. Note that all the transactions initiated to complete the data transfer are considered to be part of an
atomic transaction, so the MCU does not allow other unrelated master accesses or bus arbitration to
intervene between the transfers. If any of the transactions except the first is re-tried during an access to a
small port, then a machine-check exception is generated to the RCPU.
9-14
CLKOUT
BR
BG
BB
ADDR[8:31]
RD/WR
TSIZ[0:1]
BURST, BDIP
TS
Data
TA
Single Beat Flow with Small Port Size
Figure 9-9. Single Beat Basic Write Cycle Timing – One Wait State
O
O
MPC561/MPC563 Reference Manual, Rev. 1.2
Receive bus grant and bus busy negated
O
O
Assert BB, drive address and assert TS
Wait state
O
Data is sampled
Freescale Semiconductor

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