MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 409

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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address type match the values programmed in the BR and OR for one of the memory controller banks, the
attributes for the memory cycle are taken from the OR and BR registers. These attributes include the
following fields: CSNT, ACS, SCY, BSCY, WP, TRLX, BI, PS, and SETA.
chip-select timing options.
Byte write and read-enable signals (WE/BE[0:3]) are available for each byte that is written to or read from
memory. An output enable (OE) signal is provided to eliminate external glue logic for read cycles. Upon
system reset, a global (boot) chip select is available. (Refer to
Operation” for more information on the global chip select.) This provides a boot ROM chip select before
the system is fully configured.
The internal TA generation mode is enabled if the SETA bit in the OR register is cleared. However, if the
TA signal is asserted externally at least two clock cycles before the wait states counter has expired, this
assertion terminates the memory cycle. When SETA is cleared, it is forbidden to assert external TA less
than two clocks before the wait states counter expires.
Freescale Semiconductor
Intercycle space time
asynchronous device
Timing Attribute
Synchronous or
Access speed
Wait states
When a bank is configured for TA to be generated externally (SETA bit is
set) and the TRLX is set, the memory controller requires the external device
to provide at least one wait state before asserting TA to complete the
transfer. In this case, the minimum transfer time is three clock cycles.
SETA, TRLX
ACS, CSNT
SCY, BSCY,
Bits/Fields
EHTR
TRLX
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 10-2. Timing Attributes Summary
The TRLX (timing relaxed) bit determines strobe timing to be fast or
relaxed.
The EHTR (extended hold time on read accesses) bit is provided for
devices that have long disconnect times from the data bus on read
accesses. EHTR specifies whether the next cycle is delayed one clock
cycle following a read cycle, to avoid data bus contentions. EHTR
applies to all cycles following a read cycle except for another read cycle
to the same region.
The ACS (address-to-chip-select setup) and CSNT (chip-select
negation time) bits cause the timing of the strobes to be the same as the
address bus timing, or cause the strobes to have setup and hold times
relative to the address bus.
From zero to 15 wait states can be programmed for any cycle that the
memory controller generates. The transfer is then terminated internally.
In simplest case, the cycle length equals (2 + SCY) clock cycles, where
SCY represents the programmed number of wait states (cycle length in
clocks). The number of wait states is doubled if the TRLX bit is set (2 +
(SCY x 2)).
When the SETA (external transfer acknowledge) bit is set, TA must be
generated externally, so that external hardware determines the number
of wait states.
NOTE
Section 10.7, “Global (Boot) Chip-Select
Description
Table 10-2
summarizes the
Memory Controller
10-11

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