MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 426

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Memory Controller
10.8
The memory controller in the MPC561/MPC563 supports accesses initiated by both internal and external
bus masters to external memories. If the address of any master is mapped within the internal
MPC561/MPC563 address space, the access will be directed to the internal device, and will be ignored by
the memory controller. If the address is not mapped internally, but rather mapped to one of the memory
controller regions, the memory controller will provide the appropriate chip select and strobes as
programmed in the corresponding region (see
(EMCR)”).
The MPC561/MPC563 supports only synchronous external bus masters. This means that the external
master works with CLKOUT and implements the MPC561/MPC563 bus protocol to access a slave device.
A synchronous master initiates a transfer by asserting TS. The ADDR[0:31] signals must be stable from
the rising edge of CLKOUT during which TS is sampled, until the last TA acknowledges the transfer. Since
the external master works synchronously with the MPC561/MPC563, only setup and hold times around
the rising edge of CLKOUT are important. Once the TS is detected/asserted, the memory controller
compares the address with each one of its defined valid banks to find a possible match. But, since the
external address space is shorter than the internal space, the actual address that is used for comparing
against the memory controller regions is in the format of: {00000000, bits [8:16] of the external address}.
In the case where a match is found, the controls to the memory devices are generated and the transfer
acknowledge indication (TA) is supplied to the master.
10-28
Memory Controller External Master Support
Table 10-5. Boot Bank Fields Values After Hard Reset
BSCY[0:2]
AM[0:16]
SCY[0:3]
ATM[0:2]
ACS[0:1]
CSNT
EHTR
TRLX
SETA
Field
SST
WP
PS
BL
BI
V
MPC561/MPC563 Reference Manual, Rev. 1.2
Section 6.2.2.1.3, “External Master Control Register
0 0000 0000 0000 0000
CS3 = ID20 & ID31
Value (Binary)
RCW[4:5] BPS
CS0 = ID3
0b1111
0b011
0b1
000
00
0
0
0
0
0
0
0
Freescale Semiconductor

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