MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 429

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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10.9
The registers in
10.9.1
Freescale Semiconductor
1. In the case of an external master that accesses an internal MPC561/MPC563 module (in slave or
2. If the memory controller serves an external master, then it can support accesses to 32-bit port
3. When the SETA bit in the base register is set, then the timing programming for the various strobes
4. When configuring a chip select for a memory region with the intent to access that region
peripheral mode), if that slave device address also matches one of the memory controller’s regions,
the memory controller will not issue any CS for this access, nor will it terminate the cycle. Thus,
this practice should be avoided. Be aware also that any internal slave access prevents memory
controller operation.
devices only. This is because the MPC561/MPC563 external bus interface cannot initiate extra
cycles to complete an access to a smaller port-size device as it does not own the external bus.
(CS, OE and WE/BE) may become meaningless.
immediately after configuration, then an ISYNC instruction should be executed in order to ensure
that the configuration takes effect before any accesses are initiated.
Programming Model
General Memory Controller Programming Notes
Table 10-6
0x2F C148 — 0x2F C174
0x2F C120 — 0x13F
0x2F C10C
0x2F C11C
0x2F C100
0x2F C104
0x2F C108
0x2F C110
0x2F C114
0x2F C118
0x2F C140
0x2F C144
0x2F C178
Address
are used to control the memory controller.
Table 10-6. Memory Controller Address Map
MPC561/MPC563 Reference Manual, Rev. 1.2
Dual-Mapping Option Register (DMOR)
Dual-Mapping Base Register (DMBR)
Memory Status Register (MSTAT)
Option Register Bank 0 (OR0)
Option Register Bank 1 (OR1)
Option Register Bank 2 (OR2)
Option Register Bank 3 (OR3)
Base Register Bank 0 (BR0)
Base Register Bank 1 (BR1)
Base Register Bank 2 (BR2)
Base Register Bank 3 (BR3)
Reserved
Reserved
Register
Memory Controller
10-31

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