MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 472

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

QADC64E Legacy Mode Operation
The CCW table follows the register block in the address map. There are 64 table entries to hold the desired
analog conversion sequences. Each CCW table entry is 16-bits, with ten implemented bits in four fields.
The final block of address space belongs to the result word table, which appears in three places in the
memory map. Each result word table location holds one 10-bit conversion value.
13.3.1
The QADCMCR contains five implemented bits that control the operating modes of the QADC64E
module. The configurable modes are freeze, stop and supervisor. The QADCMCR also implements a pair
of bits that together select either legacy or enhanced mode for the QADC module, and lock that operating
mode.
13-8
.
•
SRESET
Bits
2:5
0
1
6
7
Status registers (QASR0 and QASR1) provide visibility on the status of each queue and the
particular conversion that is in progress
Field STOP FRZ
Addr
QADC64E Module Configuration Register (QADMCR)
MSB
Name
STOP
LOCK
0
FLIP
FRZ
—
1
Stop Enable. Refer to
0 = Disable stop mode
1 = Enable stop mode
Freeze Enable. Refer to
0 = Ignores the IMB3 internal FREEZE signal
1 = Finish any conversion in progress, then freeze
Reserved
Lock/Unlock QADC Mode of operation as defined by FLIP bit. Refer to
“Switching Between Legacy and Enhanced Modes of
0 = QADC mode is locked
1 = QADC mode is unlocked and changeable using FLIP bit
QADC Mode of Operation – The FLIP bit allows selection of the mode of operation of the QADC
module, either legacy mode (default) or enhanced mode. This bit can only be written when the
LOCK is set (unlocked). Refer to
Modes of
0 = Legacy mode enabled
1 = Enhanced mode enabled
Figure 13-4. Module Configuration Register (QADCMCR)
2
0000_0000
Operation,” for more information.
3
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 13-5. QADCMCR Bit Descriptions
—
0x30 4800 (QADCMCR_A); 0x30 4C00 (QADCMCR_B)
4
Section 13.3.1.1, “Low Power Stop
5
Section 13.3.1.2, “Freeze
LOCK FLIP SUPV
(Section 13.3.8, “Status Registers (QASR0 and
6
Section 13.3.1.3, “Switching Between Legacy and Enhanced
7
Description
1
8
Mode,” for more information.
9
Operation,” for more information.
Mode,” for more information.
10
11
000_0000
Section 13.3.1.3,
—
12
Freescale Semiconductor
13
14
QASR1)”)
LSB
15