MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 487

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Bits
3
4
Name
TOR1
PF2
Queue 2 Pause Flag. PF2 indicates that a queue 2 scan has reached a pause. PF2 is set
by the QADC64E when the current queue 2 CCW has the pause bit set, the selected input
channel has been converted, and the result has been stored in the result table.
Once PF2 is set, the queue enters the paused state and waits for a trigger event to allow
queue execution to continue. However, if the CCW with the pause bit set is the last CCW
in a queue, the queue execution is complete. The queue status becomes idle, not paused,
and both the pause and completion flags are set. Another exception occurs in software
controlled mode, where the PF2 can be set but queue 2 never enters the pause state.
When PF2 is set and interrupts are enabled for the corresponding queue, the QADC64E
asserts an interrupt request at the level specified by IRL2 in the interrupt register. The
software reads PF2 during an interrupt service routine to identify the interrupt request. The
interrupt request is cleared when the software writes a zero to PF2, when the bit was
previously read as a one. Once set, only software or reset can clear PF2.
PF2 is maintained by the QADC64E regardless of whether the corresponding interrupts
are enabled. The software may poll PF2 to find out when the QADC64E has reached a
pause in scanning a queue. The software acknowledges that it has detected a pause flag
being set by writing a zero to PF2 after the bit was last read as a one.
0 queue 2 has not reached a pause
1 queue 2 has reached a pause
Refer to
Queue 1 Trigger Overrun. TOR1 indicates that an unexpected trigger event has occurred
for queue 1. TOR1 can be set only while queue 1 is in the active state.
A trigger event generated by a transition on the external trigger signal or by the
periodic/interval timer may be captured as a trigger overrun. TOR1 cannot occur when the
software initiated single-scan mode or the software initiated continuous-scan mode are
selected.
TOR1 occurs when a trigger event is received while a queue is executing and before the
scan has completed or paused. TOR1 has no effect on the queue execution.
After a trigger event has occurred for queue 1, and before the scan has completed or
paused, additional queue 1 trigger events are not retained. Such trigger events are
considered unexpected, and the QADC64E sets the TOR1 error status bit. An unexpected
trigger event may be a system overrun situation, indicating a system loading mismatch.
In external gated continuous-scan mode the definition of TOR1 has been redefined. In the
case when queue 1 reaches an end-of-queue condition for the second time during an open
gate, TOR1 becomes set. This is considered an overrun condition. In this case CF1 has
been set for the first end-of-queue 1 condition and then TOR1 becomes set for the second
end-of-queue 1 condition. For TOR1 to be set, software must not clear CF1 before the
second end-of-queue 1.
The software acknowledges that it has detected a trigger overrun being set by writing a
zero to the trigger overrun, after the bit was read as a one. Once set, only software or reset
can clear TOR1.
0 No unexpected queue 1 trigger events have occurred
1 At least one unexpected queue 1 trigger event has occurred (or queue 1 reaches an
end-of-queue condition for the second time in gated mode)
Table 13-14. QASR0 Bit Descriptions (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 13-15
for a summary of pause response in all scan modes.
Description
QADC64E Legacy Mode Operation
13-23

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