MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 518

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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QADC64E Legacy Mode Operation
32-bit accesses to an even address require two bus cycles to complete the access, and two full 16-bit
QADC64E locations are accessed. The first bus cycle reads or writes the addressed 16-bit QADC64E
location and the second cycle reads or writes the following 16-bit location.
32-bit accesses to an odd address require three bus cycles. Portions of three different QADC64E locations
are accessed. The first bus cycle is treated by the QADC64E as an 8-bit access of an odd address, the
second cycle is a 16-bit aligned access, and the third cycle is an 8-bit access of an even address. The
QADC64E address space is organized into 16-bit even address locations, so a 32-bit read or write of an
odd address provides the lower half of one QADC64E location, the full 16-bit content of the following
QADC64E location, and the upper half of the third QADC64E location.
13.6
This section contains examples describing queue priority and conversion timing schemes.
13.6.1
Since there are two conversion command queues and only one A/D converter, there is a priority scheme
to determine which conversion is to occur. Each queue has a variety of trigger events that are intended to
initiate conversions, and they can occur asynchronously in relation to each other and other conversions in
progress. For example, a queue can be idle awaiting a trigger event, a trigger event can have occurred but
the first conversion has not started, a conversion can be in progress, a pause condition can exist awaiting
another trigger event to continue the queue, and so on.
The following paragraphs and figures outline the prioritizing criteria used to determine which conversion
occurs in each overlap situation.
Trigger events are described in
13-54
Trigger and Queue Interaction Examples
Queue Priority Schemes
Trigger
The situations in
S19. In each diagram, time is shown increasing from left to right. The
execution of queue 1 and queue 2 (Q1 and Q2) is shown as a string of
rectangles representing the execution time of each CCW in the queue. In
most of the situations, there are four CCWs (labeled C1 to C4) in both queue
1 and queue 2. In some of the situations, CCW C2 is presumed to have the
pause bit set, to show the similarities of pause and end-of-queue as
terminations of queue execution.
T1
T2
Events that trigger queue 1 execution (external trigger, software initiated single-scan
enable bit, or completion of the previous continuous loop)
Events that trigger queue 2 execution (external trigger, software initiated single-scan
enable bit, timer period/interval expired, or completion of the previous continuous loop)
Table
Figure 13-27
MPC561/MPC563 Reference Manual, Rev. 1.2
13-22.
Table 13-22. Trigger Events
through
NOTE
Figure 13-45
Events
are labeled S1 through
Freescale Semiconductor

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