MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 524

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

QADC64E Legacy Mode Operation
Situations S10 and S11
detected for queue 2 while the queue is suspended, the trigger overrun error bit is set, the same as if queue
2 were being executed when a new trigger event occurs. Trigger overrun on queue 2 thus permits the
software to know that queue 1 is taking up so much QADC64E time that queue 2 trigger events are being
lost.
13-60
Q1
Q2
QS
Q1
Q2
QS
0000
IDLE
0000
IDLE
Q2:
Q2:
IDLE
IDLE
T2
T2
C1
C1
ACTIVE
C1
ACTIVE
0010
(Figure 13-36
0010
C2
Q1:
C2
Q1:
T1
T1
SUSPEND
SUSPEND
C1
ACTIVE
ACTIVE
TOR2
C1
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 13-36. CCW Priority Situation 10
T2
ACTIVE
Figure 13-35. CCW Priority Situation 9
1010
1010
C2
C2
and
PF1
PF1
0110
ACT
C2
Figure
ACTIVE
C1
PF2
0110
PAUSE
0101
PAUSE
C2
PAUSE
13-37) show that when an additional trigger event is
T2
PF2
PAUS
0101
C3
ACTIVE
0110
T2
0110
C4
ACT
C3
T1
T1
SUSPEND
SUSPEND
TOR2
C3
ACTIVE
ACTIVE
C3
ACTIVE
T2
1010
1010
C4
C4
CF1
CF1
0010
ACT
C4
C3
ACTIVE
0010
CF2
C4
CF2
RESUME=1
IDLE
IDLE
Freescale Semiconductor
IDLE
0000
RESUME=0
IDLE
0000
QADC S10
QADC S9