MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 528

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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QADC64E Legacy Mode Operation
Recall QS = 0 => Queues disabled; QS = 8 => Q1 active, Q2 disabled; QS= 4 => Q1 paused, Q2 disabled.
A time separator was provided between the triggers and end of conversion (EOC). The relationship to
QCLK displayed is not guaranteed.
CWPQ1 and CWPQ2 typically lag CWP and only match CWP when the associated queue is inactive.
Another way to view CWPQ1 and CWPQ2 is that these registers update when EOC triggers the result
register to be written.
When the pause bit is set (CCW0), please note that CWP does not increment until triggered. When the
pause is not set (CCW1), the CWP increments with EOC.
The conversion results Q1 RES(x) show the result associated with CCW(x). So that R0 represents the
result associated with CCW0.
Example 2 below shows the timing for conversions in gated mode single-scan with the
same assumptions as example 1 except:
When the gate closes and opens again the conversions start with the first CCW in Q1.
When the gate closes the active conversion completes before the queue goes idle.
When Q1 completes both the CF1 bit sets and the SSE bit clears.
13-64
QCLK
Trig1
EOC
QS
CWP
CWPQ1
Q1 RES
Q1 RES shows relative result register updates
No pause bits set in any CCW
External trigger gated single-scan mode for Q1
Single-scan bit is set
LAST
0
Figure 13-46. External Trigger Mode (Positive Edge) Timing with Pause
LAST
4
8
MPC561/MPC563 Reference Manual, Rev. 1.2
CCW0
Conversion time is >= 14 QCLKS
Time between triggers
4
R0
CCW0
CCW1
8
Freescale Semiconductor
CCW1
R1
CCW2

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