MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 558

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

QADC64E Enhanced Mode Operation
14.3.6
Control register 1 is the mode control register for the operation of queue 1. The applications software
defines the queue operating mode for the queue, and may enable a completion and/or pause interrupt. All
of the control register fields are read/write data. However, the SSE1 bit always reads as zero unless the test
mode is enabled. Most of the bits are typically written once when the software initializes the QADC64E,
and not changed afterwards.
14-16
SRESET
Field CIE1
Addr
MSB
Control Register 1
Prescaler
0001111
0010000
0010001
0010010
0010011
0010100
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011100
0011101
0011110
0011111
0
[6:0]
PIE1 SSE1
1
Table 14-10. Prescaler f
f
SYSCLK
2
Div
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
3
Figure 14-10. Control Register 1 (QACR1)
MPC561/MPC563 Reference Manual, Rev. 1.2
Prescaler
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
[6:0]
0x30 480C (QACR1_A); 0x30 4C0C (QACR1_B)
4
MQ1
5
f
SYSCLK
SYSCLK
Div
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
0000_0000_0000_0000
6
Divide-by Values (continued)
Prescaler
7
1001111
1010000
1010001
1010010
1010011
1010100
1010101
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
[6:0]
8
f
9
SYSCLK
Div
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
10
Prescaler
1101111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
11
[6:0]
—
12
Freescale Semiconductor
f
SYSCLK
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Div
13
14
LSB
15