MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 578

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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QADC64E Enhanced Mode Operation
14.3.10.1 Analog Subsystem
This section describes the QADC64E analog subsystem, which includes the front-end analog multiplexer
and analog-to-digital converter.
14.3.11 Analog-to-Digital Converter Operation
The analog subsystem consists of the path from the input signals to the A/D converter block. Signals from
the queue control logic are fed to the multiplexer and state machine. The end of convert (EOC) signal and
the successive-approximation register (SAR) are the result of the conversion.
diagram of the QADC64E analog subsystem.
14.3.11.1 Conversion Cycle Times
Total conversion time is made up of initial sample time, final sample time, and resolution time. Initial
sample time refers to the time during which the selected input channel is coupled through the buffer
amplifier to the sample capacitor. This buffer is used to quickly reproduce its input signal on the sample
capacitor and minimize charge sharing errors. During the final sampling period the amplifier is bypassed,
and the multiplexer input charges the sample capacitor array directly for improved accuracy. During the
resolution period, the voltage in the sample capacitor is converted to a digital value and stored in the SAR.
Initial sample time is fixed at two QCLK cycles. Final sample time can be two or eight QCLK cycles,
depending on the value of the IST field in the CCW. Resolution time is ten QCLK cycles.
14-36
ALTREF
AN44
AN59
V
V
.
. .
RH
RL
Figure 14-20. QADC64E Analog Subsystem Block Diagram
CCW Buffer
Data Bus
CHAN
Decoder
7
10
MPC561/MPC563 Reference Manual, Rev. 1.2
Sample
REF
IST
+
-
Result
Buffer
AMP
State Mach, SAR and SAR Buffer
RDAC
(7 BIT)
7
Standard Converter Interface
CONV.
Final
Buffer
WCCW EOS/EOC
STOP
Sample
CAP Array
Equals CDAC
CRH
CRL
CDAC
(4 BIT)
4 (one is offset)
CLK
BIAS
Figure 14-20
-
+
COMP.
Zero
Freescale Semiconductor
2
shows a block

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