MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 597

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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In situation S2
trigger event is complete, the trigger overrun bit is again set, but otherwise, the additional trigger events
are ignored. After the queue is complete, the first newly detected trigger event causes queue execution to
begin again. When the trigger event rate is high, a new trigger event can be seen very soon after completion
of the previous queue, leaving software little time to retrieve the previous results. Also, when trigger events
are occurring at a high rate for queue 1, the lower priority queue 2 channels may not get serviced at all.
Situation S3
is set the same way, and that queue execution continues unchanged.
Freescale Semiconductor
Q1
Q2
QS
QS
Q1
Q2
IDLE
Q1:
(Figure
T1
(Figure
C1
TOR1
T1
IDLE
0000
ACTIVE
C2
14-26) shows that when the pause feature is in use, the trigger overrun error status bit
TOR1
T1
1000
14-25), more than one trigger event is recognized before servicing of a previous
C3
TOR1
T1
Q1:
C4
T1
CF1
IDLE
MPC561/MPC563 Reference Manual, Rev. 1.2
IDLE
C1
Figure 14-25. CCW Priority Situation 1
Figure 14-26. CCW Priority Situation 2
IDLE
TOR1
T1
T1
ACTIVE
C2
C1
1000
C3
ACTIVE
C2
1000
C4
C3
CF1
C4
0000
CF1
Q2:
T2
C1
0000
C2
ACTIVE
Q2:
T2
TOR2
0010
T2
IDLE
C3
IDLE
C1
QADC64E Enhanced Mode Operation
TOR2
C4
T2
C2
ACTIVE
CF2
0010
TOR2
C3
T2
IDLE
C4
0000
CF2
IDLE
0000
QADC S1
QADC S2
14-55

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