MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 608

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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QADC64E Enhanced Mode Operation
Each port A or B signal is configured as an input or output by programming the port data direction register
(DDRQA or DDRQB). The digital input signal states are read by the software in the upper half of the port
data register when the port data direction register specifies that the signals are inputs. The digital data in
the port data register is driven onto the port A or B signals when the corresponding bit in the port data
direction register specifies output. Refer to
Since the outputs are configured as push-pull drivers, external pull-up provisions are not necessary when
the output is used to drive another integrated circuit.
14.6.2
The QADC64E uses two external trigger signals (ETRIG[2:1]). Each of the two input external trigger
signals is associated with one of the scan queues, queue 1 or queue 2 The assignment of ETRIG[2:1] to a
queue is made in the QACR0 register by the TRG bit. When TRG=0, ETRIG1 triggers queue 1 and
ETRIG2 triggers queue 2. When TRG=1, ETRIG1 triggers queue 2 and ETRIG2 triggers queue 1.
14.6.3
V
power is required to isolate the sensitive analog circuitry from the normal levels of noise present on the
digital power supply. Refer to
The analog supply signals (V
V
14-66
DDA
RL
) and of the analog multiplexer inputs.
16 CHANNELS
and V
External Trigger Input Signals
Analog Power Signals
SSA
signals supply power to the analog subsystems of the QADC64E module. Dedicated
DDA
Figure 14-47. Equivalent Analog Input Circuitry
Appendix F, “Electrical
MPC561/MPC563 Reference Manual, Rev. 1.2
and V
SSA
) define the limits of the analog reference voltages (V
Figure 14-47
C
Appendix B, “Internal Memory
SAMPLE
P
AMP
V
V
DDA
SSA
Characteristics,” for more information.
is a diagram of the analog input circuitry.
S/H
RC DAC
Comparator
V
RH
V
RL
QADC64E 16CH SAMPLE AMP
Map” for more information.
Freescale Semiconductor
RH
and

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