MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 64

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Table
Number
Register Settings following an NMI ....................................................................................... 3-45
Machine Check Exception Processor Actions ........................................................................ 3-47
Register Settings following a Machine Check Exception ...................................................... 3-47
Register Settings following a Trace Exception....................................................................... 3-55
Register Settings following Floating-Point Assist Exceptions ............................................... 3-55
Register Settings following a Software Emulation Exception................................................ 3-56
Register Settings following an Instruction Protection Exception ........................................... 3-57
Register Settings Following a Data Protection Error Exception ............................................ 3-59
Register Settings Following a Debug Exception .................................................................... 3-60
Register Settings for Data Breakpoint Match ......................................................................... 3-60
Exception Addresses Mapping ................................................................................................. 4-9
Exception Relocation Page Offset .......................................................................................... 4-10
BBC SPRs............................................................................................................................... 4-17
Region Size Programming Possible Values............................................................................ 4-23
USIU Address Map................................................................................................................... 5-3
USIU Special-Purpose Registers .............................................................................................. 5-7
Hex Address Format for SPR Cycles ....................................................................................... 5-7
USIU Pin Multiplexing Control................................................................................................ 6-4
SGPIO Configuration ............................................................................................................... 6-7
Priority of Interrupt Sources—Regular Operation.................................................................. 6-10
Priority of Interrupt Sources—Enhanced Operation .............................................................. 6-12
Interrupt Latency Estimation for Three Typical Cases........................................................... 6-16
Decrementer Time-Out Periods .............................................................................................. 6-18
Debug Pins Configuration ...................................................................................................... 6-27
General Pins Configuration .................................................................................................... 6-27
Single-Chip Select Field Pin Configuration ........................................................................... 6-27
Settings Caused by Reset ....................................................................................................... 3-45
Register Settings following External Interrupt ...................................................................... 3-49
Register Settings for Alignment Exception ........................................................................... 3-50
Register Settings following Program Exception.................................................................... 3-52
Register Settings following a Floating-Point Unavailable Exception ................................... 3-52
Register Settings Following a Decrementer Exception ......................................................... 3-53
Register Settings following a System Call Exception ........................................................... 3-54
BBCMCR Field Descriptions ................................................................................................ 4-19
MI_RBA[0:3] Registers Bit Descriptions.............................................................................. 4-21
MI_RA[0:3] Registers Bit Descriptions ................................................................................ 4-22
MI_GRA Field Descriptions.................................................................................................. 4-24
EIBADR External Interrupt Relocation Table Base Address Register Bit Descriptions ...... 4-25
SIUMCR Bit Descriptions ..................................................................................................... 6-25
MPC561/MPC563 Reference Manual, Rev. 1.2
Tables
Title
Freescale Semiconductor
Number
Page

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