MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 645

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Queued Serial Multi-Channel Module
The SPIFIE bit in SPCR2 enables the QSPI to generate an interrupt request upon assertion of the SPIF
status flag. Because it is buffered, the value written to SPIFIE applies only upon completion of the queue
(the transfer of the entry indicated by ENDPQ). Thus, if a single sequence of queue entries is to be
transferred (i.e., no WRAP), then SPIFIE should be set to the desired state before the first transfer.
If a sub-queue is to be used, the same CPU write that causes a branch to the sub-queue may enable or
disable the SPIF interrupt for the sub-queue. The primary queue retains its own selected interrupt mode,
either enabled or disabled.
The SPIF interrupt must be cleared by clearing SPIF. Subsequent interrupts may then be prevented by
clearing SPIFIE. Clearing SPIFIE does not immediately clear an interrupt already caused by SPIF.
15.6.4.3
QSPI Flow
The QSPI operates in either master or slave mode. Master mode is used when the MCU initiates data
transfers. Slave mode is used when an external device initiates transfers. Switching between these modes
is controlled by MSTR in SPCR0. Before entering either mode, appropriate QSMCM and QSPI registers
must be initialized properly.
In master mode, the QSPI executes a queue of commands defined by control bits in each command RAM
queue entry. Chip-select pins are activated, data is transmitted from the transmit RAM and received by the
receive RAM.
In slave mode, operation proceeds in response to SS pin assertion by an external SPI bus master. Operation
is similar to master mode, but no peripheral chip selects are generated, and the number of bits transferred
is controlled in a different manner. When the QSPI is selected, it automatically executes the next queue
transfer to exchange data with the external device correctly.
Although the QSPI inherently supports multi-master operation, no special arbitration mechanism is
provided. A mode fault flag (MODF) indicates a request for SPI master arbitration. System software must
provide arbitration. Note that unlike previous SPI systems, MSTR is not cleared by a mode fault being set
nor are the QSPI pin output drivers disabled. The QSPI and associated output drivers must be disabled by
clearing SPE in SPCR1.
Figure 15-18
shows QSPI initialization.
Figure 15-19
through
Figure 15-23
show QSPI master and slave
operation. The CPU must initialize the QSMCM global and pin registers and the QSPI control registers
before enabling the QSPI for either mode of operation. The command queue must be written before the
QSPI is enabled for master mode operation. Any data to be transmitted should be written into transmit
RAM before the QSPI is enabled. During wraparound operation, data for subsequent transmissions can be
written at any time.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
15-27

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