MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 653

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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When the proper number of bits have been transferred, the QSPI stores the working queue pointer value
in CPTQP, increments the working queue pointer, and loads the next data for transfer from transmit RAM.
The command pointed to by the incremented working queue pointer is executed next, unless a new value
has been written to NEWQP. If a new queue pointer value is written while a transfer is in progress, that
transfer is completed normally.
When the CONT bit in a command RAM byte is set, PCS pins are continuously driven to specified states
during and between transfers. If the chip-select pattern changes during or between transfers, the original
pattern is driven until execution of the following transfer begins. When CONT is cleared, the data in
register PORTQS is driven between transfers. The data in PORTQS must match the inactive states of SCK
and any peripheral chip-selects used.
When the QSPI reaches the end of the queue, it sets the SPIF flag. If the SPIFIE bit in SPCR2 is set, an
interrupt request is generated when SPIF is asserted. At this point, the QSPI clears SPE and stops unless
wraparound mode is enabled.
15.6.5.1
In master mode, data transfer is synchronized with the internally-generated serial clock SCK. Control bits,
CPHA and CPOL, in SPCR0, control clock phase and polarity. Combinations of CPHA and CPOL
determine upon which SCK edge to drive outgoing data from the MOSI pin and to latch incoming data
from the MISO pin.
15.6.5.2
Baud rate is selected by writing a value from two to 255 into the SPBR field in SPCR0. The QSPI uses a
modulus counter to derive the SCK baud rate from the MCU IMB3 clock.
The following expressions apply to the SCK baud rate:
Giving SPBR a value of zero or one disables the baud rate generator. SCK is disabled and assumes its
inactive state. At reset, the SCK baud rate is initialized to one eighth of the IMB3 clock frequency.
Table 15-21
Freescale Semiconductor
provides some example SCK baud rates with a 40-MHz IMB3 clock.
Clock Phase and Polarity
Baud Rate Selection
Table 15-21. Example SCK Frequencies with a 40-MHz IMB3 Clock
Division Ratio
MPC561/MPC563 Reference Manual, Rev. 1.2
SPBR
4
6
8
SCK Baud Rate
=
-----------------------------------------------------------------------
2xSCK Baud Rate Desired
SPBR Value
or
2
3
4
=
f
SYS
---------------------- -
2xSPBR
f
SYS
Frequency
10.00 MHz
6.67 MHz
5.00 MHz
SCK
Queued Serial Multi-Channel Module
Eqn. 15-1
Eqn. 15-2
15-35

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