MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 659

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Queued Serial Multi-Channel Module
QSPI is selected it resumes storing bits in the same receive-data segment address where it left off. If more
than 16 bits are transferred before negating the PCS0/SS, the QSPI stores the number of bits indicated by
BITS in the current receive data segment address, then increments the address and continues storing as
described above.
NOTE
PCS0/SS does not necessarily have to be negated between transfers.
Once the proper number of bits (designated by BITS) are transferred, the QSPI stores the received data in
the receive data segment, stores the internal working queue pointer value in CPTQP, increments the
internal working queue pointer, and loads the new transmit data from the transmit data segment into the
data serializer. The internal working queue pointer address is used the next time PCS0/SS is asserted,
unless the CPU writes to the NEWQP first.
The DT and DSCK command control bits are not used in slave mode. As a slave, the QSPI does not drive
the clock line nor the chip-select lines and, therefore, does not generate a delay.
In slave mode, the QSPI shifts out the data in the transmit data segment. The trans-mit data is loaded into
the data serializer (refer to
Figure
15-1) for transmission. When the PCS0/SS pin is pulled low the MISO
pin becomes active and the serializer then shifts the 16 bits of data out in sequence, most significant bit
first, as clocked by the incoming SCK signal. The QSPI uses CPHA and CPOL to determine which
incoming SCK edge the MOSI pin uses to latch incoming data, and which edge the MISO pin uses to drive
the data out.
The QSPI transmits and receives data until reaching the end of the queue (defined as a match with the
address in ENDQP), regardless of whether PCS0/SS remains selected or is toggled between serial
transfers. Receiving the proper number of bits causes the received data to be stored. The QSPI always
transmits as many bits as it receives at each queue address, until the BITS value is reached or PCS0/SS is
negated.
15.6.7
Slave Wraparound Mode
When the QSPI reaches the end of the queue, it always sets the SPIF flag, whether wraparound mode is
enabled or disabled. An optional interrupt to the CPU is gen-erated when SPIF is asserted. At this point,
the QSPI clears SPE and stops unless wraparound mode is enabled. A description of SPIFIE bit can be
found in <XrefBlue>15.6.1.3 QSPI Control Register 2 (SPCR2).
In wraparound mode, the QSPI cycles through the queue continuously. Each time the end of the queue is
reached, the SPIF flag is set. If the CPU fails to clear SPIF, it remains set, and the QSPI continues to send
interrupt requests to the CPU (assuming SPIFIE is set). The user may avoid causing CPU interrupts by
clearing SPIFIE.
As SPIFIE is buffered, clearing it after the SPIF flag is asserted does not immediately stop the CPU
interrupts, but only prevents future interrupts from this source. To clear the current interrupt, the CPU must
read QSPI register SPSR with SPIF asserted, followed by a write to SPSR with zero in SPIF (clear SPIF).
Execution continues in wraparound mode even while the QSPI is requesting interrupt service from the
CPU. The internal working queue pointer is incremented to the next address and the commands are
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
15-41