MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 675

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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The operation of the receiver bit processor is shown in
search for a valid start bit and the synchronization procedure as outlined above. The possibilities of noise
durations greater than one bit-time are not considered in this examples.
15.7.7.8
The RE bit in SCCxR1 enables (RE = 1) and disables (RE = 0) the receiver. The receiver contains a receive
serial shifter and a parallel receive data register (RDRx) located in the SCI data register (SCxDR). The
serial shifter cannot be directly accessed by the CPU. The receiver is double-buffered, allowing data to be
held in the RDRx while other data is shifted in.
Receiver bit processor logic drives a state machine that determines the logic level for each bit-time. This
state machine controls when the bit processor logic is to sample the RXD pin and also controls when data
is to be passed to the receive serial shifter. A receive time clock is used to control sampling and
synchronization. Data is shifted into the receive serial shifter according to the most recent synchronization
of the receive time clock with the incoming data stream. From this point on, data movement is
synchronized with the MCU IMB3 clock. Operation of the receiver state machine is detailed in the Queued
Serial Module Reference Manual.
The number of bits shifted in by the receiver depends on the serial format. However, all frames must end
with at least one stop bit. When the stop bit is received, the frame is considered to be complete, and the
received data in the serial shifter is transferred to the RDRx. The receiver data register flag (RDRF) is set
when the data is transferred.
The stop bit is always a logic one. If a logic zero is sensed during this bit-time, the FE flag in SCxSR is
set. A framing error is usually caused by mismatched baud rates between the receiver and transmitter or
by a significant burst of noise. Note that a framing error is not always detected; the data in the expected
stop bit-time may happen to be a logic one.
Noise errors, parity errors, and framing errors can be detected while a data stream is being received.
Although error conditions are detected as bits are received, the noise flag (NF), the parity flag (PF), and
the framing error (FE) flag in SCxSR are not set until data is transferred from the serial shifter to the RDRx.
Freescale Semiconductor
1
R
T
1
*
* Restart RT Clock
1 1 1
R
T
1
* *
Receiver Functional Operation
R
T
1
R
T
1
* *
R
T
1
1
1
R
T
1
* *
1
R
T
1
1 1
R
T
1
* *
R
T
1
MPC561/MPC563 Reference Manual, Rev. 1.2
R
T
1
0
Figure 15-30. Start Search Example
R
T
2
0
R
T
3
R
T
4
Perceived Start Bit
0
R
T
5
Actual Start Bit
R
T
6
0 0
R
T
7
R
T
8
Figure
R
T
9
0 0
R
T
1
0
R
T
1
1 2
15-30. This example demonstrates the
R
T
1
R
T
1
3 4
R
T
1
R
T
1
5 6
R
T
1
*
Queued Serial Multi-Channel Module
R
T
1
R
T
2
R
T
3
LSB
15-57

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