MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 689

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Freescale Semiconductor
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be used as general purpose 9-bit registers. Software should ignore all other bits pertaining to the
queue.
Only data that has no errors (FE and PF both false) is allowed into the queue. The status flags FE
and PF, if set, reflect the status of data not allowed into the queue. The receive queue is disabled
until the error flags are cleared via the original SCI mechanism and the queue is re-initialized. The
pointer QRPNT indicates the queue location where the data frame would have been stored.
Queue size capable to receive up to 16 data frames (SCRQ[0:15]) which may allow for infinite and
continuous receives.
Interrupt generation can occur when the top half (SCRQ[0:7]) of the queue has been filled (QTHF)
and the bottom half (SCRQ[8:15]) of the queue has been filled (QBHF). This may allow for
uninterrupted and continuous receives by indicating to the CPU to start reading the queue portion
that is now full.
— The QTHF bit is set by hardware when the top half is full. The QTHF bit is cleared when the
— The QBHF bit is set by hardware when the bottom half is full. The QBHF bit is cleared when
In order to implement the receive queue, the following conditions must be met: QRE must be set
(QSCI1CR); RE must be set (SCC1R1); QOR and QTHF must be cleared (QSCI1SR); and OR,
PF, and FE must be cleared (SC1SR).
Enable and disable options for the interrupts QTHF and QBHF as controlled by the QTHFI and
QBHFI, respectfully.
4-bit counter (QRPNT) is used as a pointer to indicate where the next valid data frame will be
stored.
A queue overrun error flag (QOR) to indicate when the queue is already full when another data
frame is ready to be stored into the queue (similar to the OR bit in single buffer mode). The QOR
bit can be set for QTHF = 1 or QBHF = 1, depending on where the store is being attempted.
The queue can be exited when an idle line is used to indicate when a group of serial transmissions
is finished. This can be achieved by using the ILIE bit to enable the interrupt when the IDLE flag
is set. The CPU can then clear QRE and/or RE allowing the receiver queue to be exited.
For receiver queue operation, IDLE is cleared when SC1SR is read with IDLE set, followed by a
read of SCRQ[0:15].
For receiver queue operation, NF is cleared when the SC1SR is read with NF set, followed by a
read of SCRQ[0:15]. When noise occurs, the data is loaded into the receive queue, and operation
continues unaffected. However, it may not be possible to determine which data frame in the receive
queue caused the noise flag to be asserted.
The queue is successfully filled (16 data frames) if error flags (FE and PF) are clear, QTHF and
QBHF are set, and QRPNT is reset to all zeroes.
QOR indicates that a new data frame has been received in the data register (SC1DR), but it cannot
be placed into the receive queue due to either the QTHF or QBHF flag being set (QSCI1SR). Under
this condition, the receive queue is disabled (QRE = 0). Software may service the receive queue
and clear the appropriate flag (QTHF, QBHF). Data is not lost provided that the receive queue is
re-enabled before OR (SC1SR) is set, which occurs when a new data frame is received in the shifter
SCxSR is read with QTHF set, followed by a write of QTHF to zero.
the SCxSR is read with QBHF set, followed by a write of QBHF to zero.
MPC561/MPC563 Reference Manual, Rev. 1.2
Queued Serial Multi-Channel Module
15-71