MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 705

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Both counters are read-only (except in test/freeze/halt modes).
The TouCAN responds to any bus state as described in the CAN protocol, transmitting an error active or
error passive flag, delaying its transmission start time (error passive) and avoiding any influence on the
bus when in the bus off state. The following are the basic rules for TouCAN bus state transitions:
The three basic states and the transition behavior of the CAN controller are shown in
Freescale Semiconductor
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Following reset, both counters reset to zero
Detect values for error passive, bus off and error active transitions
Cascade usage of Tx error counter with an additional internal counter to detect the 128 occurrences
of 11 consecutive recessive bits necessary to transition from bus off into error active.
If the value of the Tx error counter or Rx error counter increments to a value greater than or equal
to 128, the fault confinement state (FCS[1:0]) field in the error status register is updated to reflect
an error passive state.
If the TouCAN is in an error passive state, and either the Tx error counter or Rx error counter
decrements to a value less than or equal to 127 while the other error counter already satisfies this
condition, the FCS[1:0] field in the error status register is updated to reflect an error active state.
If the value of the Tx error counter increases to a value greater than 255, the FCS[1:0] field in the
error status register is updated to reflect a bus off state, and an interrupt may be issued. The value
of the Tx error counter is reset to zero.
If the TouCAN is in the bus off state, the Tx error counter and an additional internal counter are
cascaded to count 128 occurrences of 11 consecutive recessive bits on the bus. To do this, the Tx
error counter is first reset to zero, and then the internal counter begins counting consecutive
recessive bits. Each time the internal counter counts 11 consecutive recessive bits, the Tx error
counter is incremented by one and the internal counter is reset to zero. When the Tx error counter
reaches the value of 128, the FCS[1:0] field in the error status register is updated to be error active,
and both error counters are reset to zero. Any time a dominant bit is detected following a stream of
less than 11 consecutive recessive bits, the internal counter resets itself to zero but does not affect
the Tx error counter value.
If only one node is operating in a system, the Tx error counter is incremented with each message
it attempts to transmit, due to the resulting acknowledgment errors. However, acknowledgment
errors never cause the TouCAN to change from the error passive state to the bus off state.
If the Rx error counter increments to a value greater than 127, it stops incrementing, even if more
errors are detected while being a receiver. After the next successful message reception, the counter
is reset to a value between 119 and 127, to enable a return to the error active state.
MPC561/MPC563 Reference Manual, Rev. 1.2
CAN 2.0B Controller Module
Figure
16-6.
16-11