MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 719

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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16.7.1
Freescale Semiconductor
SRESET
Bits
Field STOP FRZ
Addr
0
1
2
3
4
5
TouCAN Module Configuration Register (CANMCR)
MSB
WAKEMSK
0
NOTRDY
Name
STOP
HALT
FRZ
1
Figure 16-9. TouCAN Module Configuration Register (CANMCR)
0x30 7080 (CANMCR_A); 0x30 7480 (CANMCR_B); 0x30 7880 (CANMCR_C)
Low-power stop mode enable. The STOP bit may only be set by the CPU. It may be cleared
either by the CPU or by the TouCAN, if the SELFWAKE bit is set.
Before asserting the STOP Mode, the CPU should disable all interrupts in the TOUCAN,
otherwise it may be interrupted while in STOP mode upon a non wake-up condition.
WAKE-INT can still be enabled by setting WAKEMSK.
0 Enable TouCAN clocks
1 Disable TouCAN clocks
FREEZE assertion response. When FRZ = 1, the TouCAN can enter debug mode when the
IMB3 FREEZE line is asserted or the HALT bit is set. Clearing this bit field causes the
TouCAN to exit debug mode. Refer to
0 TouCAN ignores the IMB3 FREEZE signal and the HALT bit in the module configuration
1 TouCAN module enabled to enter debug mode.
Reserved
Halt TouCAN S-Clock. Setting the HALT bit has the same effect as assertion of the IMB3
FREEZE signal on the TouCAN without requiring that FREEZE be asserted. This bit is set to
one after reset. It should be cleared after initializing the message buffers and control
registers. TouCAN message buffer receive and transmit functions are inactive until this bit is
cleared.
When HALT is set, write access to certain registers and bits that are normally read-only is
allowed.
0 The TouCAN operates normally
1 TouCAN enters debug mode if FRZ = 1
TouCAN not ready. This bit indicates that the TouCAN is either in low-power stop mode or
debug mode. This bit is read-only and is set only when the TouCAN enters low-power stop
mode or debug mode. It is cleared once the TouCAN exits either mode, either by
synchronization to the CAN bus or by the self wake mechanism.
0 TouCAN has exited low-power stop mode or debug mode.
1 TouCAN is in low-power stop mode or debug mode.
Wakeup interrupt mask. The WAKEMSK bit enables wake-up interrupt requests.
0 Wake up interrupt is disabled
1 Wake up interrupt is enabled
2
register.
HALT NOT
3
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 16-11. CANMCR Bit Descriptions
RDY
4
WAKE
MSK
5
0101_1001_1000_0000
SOFT
RST
6
ACK
FRZ
7
Section 16.5.1, “Debug
Description
SUPV SELF
8
WAKE
9
APS
10
Mode” for more information.
STOP
ACK
11
CAN 2.0B Controller Module
12
13
14
LSB
15
16-25

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