MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 73

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC562MZP56
Manufacturer:
FREESCAL
Quantity:
204
Part Number:
MPC562MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC562MZP56
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
MPC562MZP56
Quantity:
1 500
Part Number:
MPC562MZP56R2
Manufacturer:
RFT
Quantity:
1 441
Part Number:
MPC562MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
24-1
24-2
24-3
24-4
24-5
24-6
24-7
24-8
24-9
24-10
24-11
24-12
24-13
24-14
24-15
24-16
24-17
24-18
24-19
24-20
24-21
24-22
24-23
24-24
24-25
24-26
24-27
24-28
24-29
24-30
24-31
24-32
24-33
24-34
24-35
25-1
25-2
25-3
A-1
Freescale Semiconductor
Table
Number
Public Messages...................................................................................................................... 24-5
Vendor-Defined Messages...................................................................................................... 24-5
Terms and Definitions ............................................................................................................ 24-6
OTR Bit Descriptions ............................................................................................................. 24-9
Tool-Mapped Register Space.................................................................................................. 24-9
DID Bit Descriptions ............................................................................................................ 24-10
DC Bit Descriptions.............................................................................................................. 24-11
RCPU Development Access Modes ..................................................................................... 24-11
MC Bit Descriptions ............................................................................................................. 24-12
UBA Bit Descriptions ........................................................................................................... 24-13
RWA Read/Write Access Bit Descriptions .......................................................................... 24-14
UDI Bit Descriptions ............................................................................................................ 24-16
Read Access Status ............................................................................................................... 24-16
Write Access Status .............................................................................................................. 24-16
DTA 1 AND 2 Bit Descriptions ........................................................................................... 24-17
Data Trace Values................................................................................................................. 24-18
Description of READI Signals ............................................................................................. 24-21
MSEI/MSEO Protocol .......................................................................................................... 24-23
Public Messages Supported .................................................................................................. 24-24
Error Message Codes ............................................................................................................ 24-27
Vendor-Defined Messages Supported .................................................................................. 24-27
Message Field Sizes
Indirect Branch Message ...................................................................................................... 24-33
Direct Branch Message ......................................................................................................... 24-33
READI Reset Configuration Options ................................................................................... 24-34
Bit Pointer Format ................................................................................................................ 24-39
Program Trace Correction Due to a Mispredicted Branch ................................................... 24-40
Program Trace Correction Due to an Exception................................................................... 24-41
Resource Codes..................................................................................................................... 24-46
Special L-Bus Case Handling ............................................................................................... 24-56
Throughput Comparison for FPM and RPM MDO/MDI Configurations ............................ 24-68
Watchpoint Source................................................................................................................ 24-73
Development Port Access: DSDI Field ................................................................................ 24-84
Development Port Access: DSDO Field............................................................................... 24-84
Power Management Mechanism Overview .......................................................................... 24-86
MPC561 Boundary Scan Bit Definition ................................................................................. 25-5
MPC563 Boundary Scan Bit Definition ............................................................................... 25-17
Instruction Decoding............................................................................................................. 25-30
ICTRL Bit Descriptions......................................................................................................... A-17
,
............................................................................................................. 24-29
MPC561/MPC563 Reference Manual, Rev. 1.2
Tables
Title
Number
Page
lxxiii

Related parts for MPC562MZP56