MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 748

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Modular Input/Output Subsystem (MIOS14)
17.7
The MIOS14 counter prescaler submodule (MCPSM) divides the MIOS14 clock (f
counter clock. It is designed to provide all the submodules with the same division of the main MIOS14
clock (division of f
of the clock prescaler register into the prescaler counter every time it overflows. This allows all prescaling
factors between 2 and 16. Counting is enabled by asserting MCPSMSCR[PREN]. The counter can be
stopped at any time by negating this bit, thereby stopping all submodules using the output of the MCPSM
(counter clock). A block diagram of the MCPSM is given in
The following sections describe the MCPSM in detail.
17.7.1
17-16
Bits
9:15
8
Centralized counter clock generator
MIOS14 Counter Prescaler Submodule (MCPSM)
MCPSM Features
Name
SUPV
MCPSMSCR
SYS
Prescaler
Register
Clock
). It uses a 4-bit modulus counter. The clock signal is prescaled by loading the value
Supervisor data space selector — The SUPV bit tells if the address space from 0x30 6000 to
0x30 67FF in the MIOS14 is accessed at the supervisor privilege level (See
cleared, these addresses are accessed at the unrestricted privilege level.
The SUPV bit is cleared by reset.
0 Unrestricted Data Space.
1 Supervisor Data Space.
Reserved. These bits are used for the IARB (interrupt arbitration ID) field in MIOS14
implementations that use hardware interrupt arbitration. These bits are not used on
MPC561/MPC563.
Table 17-5. MIOS14MCR Bit Descriptions (continued)
PREN
f
CP0
CP1
CP2
CP3
SYS
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 17-8. MCPSM Block Diagram
Enable
Decrementer
4-bit
Dec.
Load
Description
Figure
Overflow
= 1?
17-8.
SYS
Freescale Semiconductor
Figure
Counter Clock
) to generate the
17-2). When

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