MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 766

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Modular Input/Output Subsystem (MIOS14)
The output flip-flop is set when a match occurs on channel A. The output flip-flop is reset when a match
occurs on channel B. The polarity of the output signal is selected by the EDPOL bit. The output flip-flop
level can be obtained at any time by reading the PIN bit.
If subsequent enabled output compares occur on channels A and B, the output pulses continue to be output,
regardless of the state of the FLAG bit.
At any time, the FORCA and FORCB bits allow the software to force the output flip-flop to the level
corresponding to a comparison on channel A or B, respectively.
Totem pole or open-drain output circuit configurations can be selected using the WOR bit in the
MDASMSCR register.
17.9.3.5.1
The single shot output pulse operation is selected by writing the leading edge value of the desired pulse to
data register A and the trailing edge value to data register B. A single pulse will be output at the desired
time, thereby disabling the comparators until new values are written to the data registers. To generate a
single shot output pulse, the OCB mode should be used to only generate a flag on the B match.
In this mode, registers A and B2 are accessible to the user software (at consecutive addresses).
Figure 17-19
17-34
provides an example of how the MDASM can be used to generate a single output pulse.
The FLAG line is not affected by these ‘force’ operations.
If both channels are loaded with the same value, the output flip-flop
provides a logic zero level output and the flag bit is still set on the match.
16-bit counter bus compare only occurs when the 16-bit counter bus is
updated.
Single Shot Output Pulse Operation
MPC561/MPC563 Reference Manual, Rev. 1.2
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