MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 787

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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A value must be written to the MPWMCNTR (which writes the same value into the MPWMPERR) and a
pulse width value written to MPWMPULR, before the MPWMSCR is written to. The latter access
initializes the clock prescaler.
17.10.6 MPWMSM Registers
The privilege level to access to the MPWMSM registers depends on the MIOS14MCR[SUPV]. The
privilege level is unrestricted after reset and can be change to supervisor by software.
17.10.6.1 MPWMSM Registers Organization
The MPWMSM register map comprises four 16-bit register locations, as shown in
bits return zero when read by the software. All register addresses in this section are specified as offsets
from the base address of the MPWMSM.
Freescale Semiconductor
0x30 600C
0x30 6000
0x30 6002
0x30 6004
0x30 6006
0x30 6008
0x30 600A
0x30 600E
0x30 6010
0x30 6012
0x30 6014
0x30 6016
0x30 6018
0x30 601A
Address
MPWMSM0 Period Register (MPWMPERR)
See
MPWMSM0 Pulse Register (MPWMPULR)
See
MPWMSM0 Count Register (MPWMCNTR)
See
MPWMSM0 Status/Control Register (MPWMSCR)
See
MPWMSM1 Period Register (MPWMPERR)
MPWMSM1 Pulse Register (MPWMPULR)
MPWMSM1 Count Register (MPWMCNTR)
MPWMSM1 Status/Control Register (MPWMSCR)
MPWMSM2 Period Register (MPWMPERR)
MPWMSM2 Pulse Register (MPWMPULR)
MPWMSM2 Count Register (MPWMCNTR)
MPWMSM2 Status/Control Register (MPWMSCR)
MPWMSM3 Period Register (MPWMPERR)
MPWMSM3 Pulse Register (MPWMPULR)
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 17-26
Table 17-27
Table 17-28
Table 17-29
Table 17-25. MPWMSM Address Map
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
MPWMSM0
MPWMSM1
MPWMSM2
MPWMSM3
Register
Modular Input/Output Subsystem (MIOS14)
Table
17-25. All unused
17-55

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