MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 794

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Modular Input/Output Subsystem (MIOS14)
17.11.4 Modular I/O Bus (MIOB) Interface
17.11.5 Effect of RESET on MPIOSM
When the RESET signal is asserted, all the DDR bits are cleared. The data bits are undefined after reset.
17.11.6 MPIOSM Testing
No special test logic has been implemented in this submodule. To be flexible while selecting the number
of implemented signals, the test patterns are implemented in a bit per bit modular fashion.
17.11.7 MPIOSM Registers
The privilege level to access to the MPIOSM registers depends on the MIOS14MCR[SUPV]. The
privilege level is unrestricted after reset and can be change to supervisor by software.
17.11.8 MPIOSM Register Organization
17.11.8.1 MPIOSM Data Register (MPIOSMDR)
17-62
•
•
•
0x30 6100
0x30 6102
0x30 6104
0x30 6106
SRESET
The MPIOSM is connected to all the signals in the read/write and control bus, to allow data transfer
from and to the MPIOSM registers, and to control the MPIOSM in the different possible situations.
The MPIOSM does not use the counter bus set and is therefore not connected to it.
The MPIOSM does not generate any interrupts and is therefore not connected to this bus.
Field Data
Addr
MSB
15
MSB
0
0
Data
14
1
1
Data
13
2
2
Figure 17-32. MPIOSM Data Register (MPIOSMDR)
Figure 17-31. MPIOSM — Register Organization
Data
12
3
3
MPC561/MPC563 Reference Manual, Rev. 1.2
Data
11
4
MPIOSM Data Direction Register (MPIOSMDDR)
4
Data
MPIOSM Data Register (MPIOSMDR)
10
5
5
Data
9
6
6
Data
0x30 6100
Undefined
Reserved
Reserved
8
7
7
Data
7
8
8
Data
6
9
9
Data
10
10
5
Data
11
11
4
Data
12
12
3
Freescale Semiconductor
Data
13
13
2
Data
14
14
1
Data
LSB
15
15
0