MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 801

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

17.12.5 Interrupt Control Section (ICS)
The interrupt control section delivers the interrupt level to the CPU. The interrupt control section adapts
the characteristics of the MIOB request bus to the characteristics of the interrupt structure of the IMB3.
When at least one of the flags is set on an enabled level, the ICS receives a signal from the corresponding
IRQ pending register. This signal is the result of a logical “OR” between all the bits of the IRQ pending
register.
The signal received from the IRQ pending register is associated with the interrupt level register within the
ICS. This level is coded on five bits in this register: three bits represent one of eight levels and the two
other represent the four time multiplex slots. According to this level, the ICS sets the correct IRQ[7:0] lines
with the correct ILBS[1:0] time multiplex lines on the peripheral bus. The CPU is then informed as to
which of the thirty-two interrupt levels is requested.
Based on the interrupt level requested, the software must determine which submodule requested the
interrupt. The software may use a find-first-one type of instruction to determine, in the concerned MIRSM,
which of the bits is set. The CPU can then serve the requested interrupt.
17.12.6 MBISM Interrupt Registers
Table 17-41
17.12.6.1 MIOS14 Interrupt Level Register 0 (MIOS14LVL0)
This register contains the interrupt level that applies to the submodules numbers 15 to zero.
Freescale Semiconductor
SRESET
10:15
Bits
Field
7:9
Addr
shows the MBISM interrupt registers.
MSB
IRP24:22 Pending Bits — MMCSM pending bits [24:22]
IRP21:16 Pending Bits — PWMSM pending bits [21:16]
0
Name
0x30 6C30
0x30 6C70
Address
1
Figure 17-41. MIOS14 Interrupt Level Register 0 (MIOS14LVL0)
—
Table 17-40. MIOS14RPR1 Bit Descriptions (continued)
2
Table 17-41. MBISM Interrupt Registers Address Map
MIOS14 Interrupt Level Register 0 (MIOS14LVL0)
See
MIOS14 Interrupt Level Register 1 (MIOS14LVL1)
See
3
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 17-42
Table 17-43
4
5
for bit descriptions.
for bit descriptions.
LVL
0000_0000_0000_0000
6
0x30 6C30
7
Register
Description
8
TM
9
10
Modular Input/Output Subsystem (MIOS14)
11
12
—
13
14
LSB
15
17-69