MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 802

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Modular Input/Output Subsystem (MIOS14)
17.12.6.2 MIOS14 Interrupt Level Register 1 (MIOS14LVL1)
This register contains the interrupt level that applies to the submodules number 15 to zero.
17.13 MIOS14 Function Examples
The versatility of the MIOS14 timer architecture is based on multiple counters and capture/compare
channel units interconnected on 16-bit counter buses. This section includes some typical application
examples to show how the submodules can be interconnected to form timing functions. The diagrams used
to illustrate these examples show only the blocks utilized for that function.
To illustrate the timing range of the MIOS14 in different applications, many of the following paragraphs
include time intervals quoted in microseconds and seconds. The assumptions used are that f
MHz with minimum overall prescaling (50 ns cycle) and with the maximum overall prescaling (32 µs
cycle). For other f
scale appropriately.
17.13.1 MIOS14 Input Double Edge Pulse Width Measurement
To measure the width of an input pulse, the MIOS14 double action submodule (MDASM) has two capture
registers so that only one interrupt is needed after the second edge. The software can read both edge
17-70
SRESET
10:15
10:15
Bits
Bits
0:4
5:7
8:9
0:4
5:7
8:9
Field
Addr
MSB
Name
Name
0
LVL
LVL
TM
TM
SYS
1
Figure 17-42. MIOS14 Interrupt Level Register 1 (MIOS14LVL1)
clock cycle rates and prescaler choices, the times mentioned in these paragraphs
Reserved
Interrupt request level. This field represents one of eight possible levels.
Time multiplexing. This field determines the multiplexed time slot
Reserved
Reserved
Interrupt request level. This field represents one of eight possible levels.
Time multiplexing. This field determines the multiplexed time slot.
Reserved
2
3
Table 17-42. MIOS14LVL0 Bit Descriptions
Table 17-43. MIOS14LVL1 Bit Descriptions
MPC561/MPC563 Reference Manual, Rev. 1.2
4
5
LVL
0000_0000_0000_0000
6
0x30 6C70
7
Description
Description
8
TM
9
10
11
12
Freescale Semiconductor
13
SYS
14
is at 40
LSB
15

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