MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 822

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Peripheral Pin Multiplexing (PPM) Module
TX_CONFIG_1 and TX_CONFIG_2 can only be written while PPM transmit mode is disabled
(PPMPCR[ENTX] = 0). While transmit is enabled these registers read as 0x00 and writing them will return
TEA (bus error access).
18.4.4
The two receive configuration registers control which internal modules will receive data from the PPM.
Each of the configuration registers contains eight separate 2-bit wide bit fields. Each of the 16 fields
controls a multiplexer that selects a 1-bit channel from the PPM data receive register to an internal module.
See
RX_CONFIG_1 and RX_CONFIG_2 can only be written while PPM receive mode is disabled
(PPMPCR[ENRX] = 0). While receive mode is enabled these registers read as 0x00 and writing them will
return TEA (bus error access).
18-16
SRESET
SRESET
SRESET
Table 18-6
Field
Field
Addr
Addr
Field
Addr
Receive Configuration Registers (RX_CONFIG_1 and
RX_CONFIG_2)
MSB
MSB
MSB
0
0
0
CH15
CH7
CH7
for more information on channel control and setting the channel values.
1
1
1
Figure 18-14. Transmit Configuration Register 1 (TX_CONFIG_1)
Figure 18-15. Transmit Configuration Register 2 (TX_CONFIG_2)
Figure 18-16. Receive Configuration Register 1 (RX_CONFIG_1)
2
2
2
CH14
CH6
CH6
3
3
3
MPC561/MPC563 Reference Manual, Rev. 1.2
4
4
4
CH13
CH5
CH5
5
5
5
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
6
6
6
CH12
CH4
CH4
0x30 5C06
0x30 5C08
0x30 5C0E
7
7
7
8
8
8
CH11
CH3
CH3
9
9
9
10
10
10
CH10
CH2
CH2
11
11
11
12
12
12
CH9
CH1
CH1
Freescale Semiconductor
13
13
13
14
14
14
CH0
CH8
CH0
LSB
LSB
LSB
15
15
15