MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 832

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Time Processor Unit 3
19.1
The TPU3 can be viewed as a special-purpose microcomputer that performs a programmable series of two
operations, match and capture. Each occurrence of either operation is called an event. A programmed
series of events is called a function. TPU functions replace software functions that would require CPU
interrupt service.
The microcode ROM TPU3 functions that are available in the MPC561/MPC563 are described in
Appendix D, “TPU3 ROM
19.2
The TPU3 consists of two 16-bit time bases, 16 independent timer channels, a task scheduler, a
microengine, and a host interface. In addition, a dual-ported parameter RAM (DPTRAM) is used to pass
parameters between the module and the CPU.
19.2.1
Two 16-bit counters provide reference time bases for all output-compare and input-capture events.
Prescalers for both time bases are controlled by the CPU via bit fields in the TPU3 module configuration
register (TPUMCR) and TPU module configuration register two (TPUMCR2). Timer count registers
TCR1 and TCR2 provide access to the current counter values. TCR1 and TCR2 can be read by TPU
microcode but are not directly available to the CPU. The TCR1 clock is always derived from the system
clock. The TCR2 clock can be derived from the system clock or from an external input via theT2CLK
clock pin. The duration between active edges on the T2CLK clock pin must be at least nine system clocks.
19.2.2
The TPU3 has 16 independent channels, each connected to an MCU pin. The channels have identical
hardware and are functionally equivalent in operation. Each channel consists of an event register and pin
control logic. The event register contains a 16-bit capture register, a 16-bit compare/match register, and a
16-bit greater-than-or-equal-to comparator. The direction of each pin, either output or input, is determined
by the TPU microengine. Each channel can either use the same time base for match and capture, or can
use one time base for match and the other for capture.
19.2.3
When a service request is received, the scheduler determines which TPU3 channel is serviced by the
microengine. A channel can request service for one of four reasons: for host service, for a link to another
channel, for a match event, or for a capture event. The host system assigns each active channel one of three
priorities: high, middle, or low. When multiple service requests are received simultaneously, a
priority-scheduling mechanism grants service based on channel number and assigned priority.
19-2
Overview
TPU3 Components
Time Bases
Timer Channels
Scheduler
Functions.”
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor