MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 868

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

CDR3 Flash (UC3F) EEPROM
21-6
Bits
0
1
2
3
4
LOCK
Name
STOP
FIC
SIE
—
1
Array stop control. Writes to the STOP bit have no effect while in program or erase operation
(SES = 1). The STOP bit is always readable whenever the registers are enabled.
When STOP = 1, the reset state of STOP is 1 and the UC3F array is disabled; internal circuits are
switched into a low power state. The STOP bit may be used to implement low power standby
modes or power management schemes. The UC3FMCR remains readable and writable when
STOP = 1 so that the STOP bit may be deasserted. Attempts to program or erase the array while
STOP = 1 have no effect. SES cannot be set to 1 when STOP = 1.
When STOP = 0, the reset state of STOP is 0 and the UC3F array is enabled for accesses. All
registers that were disabled with STOP = 1 are now enabled. A STOP recovery time of 1 µs is
required for biases in the UC3F array to reach their appropriate states to resume normal operation.
Operations to the UC3F array should be delayed for at least 1µs after clearing the STOP bit.
0 = UC3F array is enabled
1 = UC3F array is disabled (low-power mode)
Lock control. The default reset state of LOCK is 1. This enables writing of all fields in the Flash
registers.
Once the LOCK bit has been asserted (LOCK = 0) in normal operating mode, the write-lock can
only be disabled again by a reset. When the device is in background debug mode and CSC = 0,
the LOCK bit may be written from a 0 to a 1.
When the LOCK control bit is cleared to 0, the write-locked register bits: FIC, SUPV, SBSUPV[0:1],
DATA, SBDATA, PROTECT, SBPROTECT, and SBEN[0:1] are locked. Writes to these bits while
LOCK = 0 will have no effect.
LOCK can be written to 0 once after reset when UC3FCTL[CSC] = 0 to allow protection of the
write-locked register bits after initialization.
Reserved
Force information censorship. The default reset state of FIC is normal censorship operation
(FIC = 0). The FIC bit is write protected by the LOCK bit and the UC3FCTL[CSC] bit. Writes will
have no effect if LOCK = 0 or CSC = 1. Once FIC is set (FIC = 1), it cannot be cleared except by
a reset. The FIC bit can be read whenever the registers are enabled.
The FIC bit is a censorship emulation mode used to aid in the development of custom techniques
for controlling the ACCESS bit without setting CENSOR[0:1] to the information censorship state.
Using FIC to force information censorship allows testing of the hardware and software for setting
ACCESS without setting CENSOR[0:1] = 11 and risk permanently setting the device into an
unusable information censorship state.
0 = normal uc3f censorship operation
1 = forces the uc3f into information censorship mode
Shadow information enable. The default reset state of SIE is 0. The SIE bit is write protected in
program operation (SES = 1 and PE = 0). The SIE bit can be read whenever the registers are
enabled.
When SIE = 1, normal array accesses are disabled, and the two shadow information rows are
enabled. Array accesses are directed to the shadow row while SIE = 1. When an array location is
read in this mode, only the lower 6 address bits are used to select which 64 bytes of the 512-byte
shadow row are read. The upper address bits are not used for shadow row decoding. The read
page buffer address monitor is reset whenever SIE is modified making the next UC3F array access
an off page access.
0 = normal array access
1 = disables normal array access and selects the shadow information rows
If the lock protection mechanism is enabled (LOCK = 0) before PROTECT and
SBPROTECT are cleared, the device must use background debug mode to
program or erase the UC3F EEPROM.
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 21-3. UC3FMCR Bit Descriptions
Description
WARNING:
Freescale Semiconductor