MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 88

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Overview
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1.3.1.3
1-4
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PowerPC
Precise exception model
64-bit floating point unit (FPU)
Code compression supported on MPC562/MPC564
Reduces usage of internal/external Flash memory (up to 50% for code) on the MPC564
Reduces code size up to 50%
Extensive system development support
On-chip watchpoints and breakpoints
Program flow tracking capability
System configuration and protection features:
— Periodic-interrupt timer
— Bus monitor
— Software watchdog timer
— Real-time clock (RTC)
— PPC decrementer
— Time base
Clock synthesizer
Power management
Reset controller
External bus interface that tolerates 5-V inputs, provides 2.6-V outputs, and supports multi-master
designs
Enhanced interrupt controller that supports up to eight external and 40 internal interrupts,
simplifies the interrupt structure, and decreases interrupt processing time
USIU supports dual mapping to map part of one internal/external memory to another external
memory
External bus, supporting non-wraparound burst for instruction fetches, with up to 8 instructions per
memory cycle
Support for enhanced interrupt controller (EIC)
Support for enhanced exception table relocation feature
Branch target buffer
Contains 2 Kbytes of decompression RAM (DECRAM) for code compression. This RAM may
also be used as general-purpose RAM when the code compression feature is not used.
RISC MCU Central Processing Unit (RCPU)
Unified System Interface Unit (USIU)
Burst Buffer Controller (BBC) Module
ΤΜ
-compliant 32-bit single issue core
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor