MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 894

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

CDR3 Flash (UC3F) EEPROM
21.3.11.2 Setting Censor
The set operation changes the state in an NVM CAM cell from a 0 to a 1. This set operation can be done
without changing the contents of the UC3F array. The required sequence to set one or both of the bits in
CENSOR[0:1] follows.
21.3.11.3 Clearing Censor
The clear operation changes the state of the CENSOR[0:1] bits from a 1 to a 0 by erasing the CAM cells.
This clear operation can be done only while erasing the entire UC3F array and shadow information. The
required sequence to clear CENSOR follows.
Clear CENSOR[0:1]
21-32
1. Write CSC = 1, PE = 0 and SES = 1 in the UC3FCTL register
2. Write a 1 to the CENSOR bit(s) to be set
3. Write EHV = 1 in the UC3FCTL register
4. Read the UC3FCTL register until HVS = 0
5. Read the UC3FCTL register. Confirm PEGOOD = 1
6. Write EHV = 0 in the UC3FCTL register
7. Write SES = 0 and CSC = 0
1. Write PROTECT[0:7] = 0x00 to enable the entire array for erase. If SBEN[M] = 1, then
2. Write BLOCK[0:7] = 0xFF, CSC = 1, PE = 1 and SES = 1 in the UC3FCTL register. If SBEN[M]
3. Do an erase interlock write.
4. Write EHV = 1 in the UC3FCTL register.
SBPROTECT[M] must also be cleared to 0.
= 1, then SBBLOCK[M] must also be set to 1.
On the UC3F module, the erase interlock write can be performed in one of two ways, depending
on the value of the UC3FCFIG bit 15, IWS.
If IWS = 0, a valid erase interlock write is a write to any valid array location. This is subject to any
censorship conditions that might apply.
If IWS = 1, a valid erase interlock write can be a write to any valid array location or a write to the
UC3FCMCR register.
When the IWS = 1, the CENSOR[0:1] bits can always be cleared in the UC3F flash EEPROM
status states #3, #4 and #5 from
The erase interlock write is only valid if all blocks of the array are selected for erase and not
protected. BLOCK[0:7] and SBBLOCK[0:1] set to 1, as well as PROTECT[0:7] and
SBPROTECT[0:1] set to 0, are required for a valid erase interlock write during the clear censor
operation.
MPC561/MPC563 Reference Manual, Rev. 1.2
Table
21-10.
Freescale Semiconductor