MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 946

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Development Support
Note: DSCK and DSDI transitions are not required to be synchronous with CLKOUT.
23-32
DSDO
DSCK
DSDI
CLKOUT
DSDO
DSDI
Debug Port drives “ready” bit onto DSDO when ready for a new transmission.
Debug Port drives “ready” bit onto DSDO when CPU starts a read of DPIR or DPDR.
Figure 23-10. Synchronous Self Clock Serial Communication
READY
Figure 23-9. Asynchronous Clock Serial Communications
READY
START
Development Tool drives the “start” bit on DSDI (after detecting “ready” bit on
DSDO when in debug mode). The “start” bit is immediately followed by
a mode bit and a control bit and then 7 or 32 input data bits.
Development Tool drives the “start” bit on DSDI (after detecting “ready” bit on
DSDO when in debug mode). The “start” bit is immediately followed by
a mode bit and a control bit and then 7 or 32 input data bits.
START
MPC561/MPC563 Reference Manual, Rev. 1.2
MODE
S<0> S<1>
S<0>
MODECNTRLDI<0>
Debug Port detects the “start” bit on DSDI and follows
the “ready” bit with two status bits and 7 or 32 output data bits.
CNTRL
Debug Port detects the “start” bit on DSDI and follows
the “ready” bit with two status bits and 7 or 32 output data bits.
S<1>
DO
<0 >
DO<0>
DI<0>
DI<1>
DO
<1 >
DI<
<N-3>
<N-3>
1
DO
<N-2>
<N-2>
DI
DO
DI
<N-2>
<N-2>
DO
DI
<N-1>
<N-1>
DO
<N-1>
DI
<N-1>
DO
DI
<N>
DO
<N>
<N>
<N>
DO
DI
DI
Freescale Semiconductor

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