MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 947

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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23.4.6.5
When not in debug mode the development port starts communications by setting DSDO (the MSB of the
35-bit development port shift register) low to indicate that all activity related to the previous transmission
are complete and that a new transmission may begin. The start of a serial transmission from an external
development tool to the development port is signaled by a start bit. A mode bit in the transmission defines
the transmission as either a trap enable mode transmission or a debug mode transmission. If the mode bit
is set the transmission will only be 10 bits long and only seven data bits will be shifted into the shift
register. These seven bits will be latched into the TECR. A control bit determines whether the data is
latched into the trap enable and VSYNC bits of the TECR or into the breakpoints bits of the TECR.
23.4.6.6
The development port shift register is 35 bits wide but trap enable mode transmissions only use the
start/ready bit, a mode/status bit, a control/status bit, and the seven least significant data bits. The encoding
of data shifted into the development port shift register (through the DSDI pin) is shown in
Table 23-11
Freescale Semiconductor
CLKOUT
SRESET
First Start bit detected after DSDI negation (self clocked mode)
CLKEN
Internal clock enable signal asserts 8 clocks after SRESET
DSDI
negation if DSDI is negated. This enables clocked mode.
below:
Development Port Serial Communications — Trap Enable Mode
Serial Data into Development Port — Trap Enable Mode
DSDI negates following SRESET negation
to enable clocked mode.
0
1
Figure 23-11. Enabling Clock Mode Following Reset
2
MPC561/MPC563 Reference Manual, Rev. 1.2
3
4
5
6
7
8
9
10
11
12
13 14
15
Development Support
Table 23-10
23-33
and

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