AT32UC3A0128-ALUR Atmel, AT32UC3A0128-ALUR Datasheet - Page 451
AT32UC3A0128-ALUR
Manufacturer Part Number
AT32UC3A0128-ALUR
Description
MCU AVR32 128K FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A0128-ALUR
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Package
144LQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
66 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
69
Interface Type
Ethernet/I2S/JTAG/SPI/TWI/USART
Number Of Timers
3
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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29.6
29.6.1
29.6.1.1
29.6.1.2
Figure 29-2. Receive Buffer List
32058J–AVR32–04/11
Programming Interface
Initialization
Configuration
Receive Buffer List
Receive Buffer Queue Pointer
(MAC Register)
Initialization of the MACB configuration (e.g. frequency ratios) must be done while the transmit
and receive circuits are disabled. See the description of the network control register and network
configuration register later in this document.
Receive data is written to areas of data (i.e., buffers) in system memory. These buffers are listed
in another data structure that also resides in main memory. This data structure (receive buffer
queue) is a sequence of descriptor entries as defined in
page
To create the list of buffers:
1. Allocate a number (n) of buffers of 128 bytes in system memory.
2. Allocate an area 2n words for the receive buffer descriptor entry in system memory and
3. If less than 1024 buffers are defined, the last descriptor must be marked with the wrap bit
4. Write address of receive buffer descriptor entry to MACB register receive_buffer queue
5. The receive circuits can then be enabled by writing to the address recognition registers
create n entries in this list. Mark all entries in this list as owned by MACB, i.e., bit 0 of
word 0 set to 0.
(bit 1 in word 0 set to 1).
pointer.
and then to the network control register.
440. It points to this data structure.
Receive Buffer Descriptor List
(In memory)
”Receive Buffer Descriptor Entry” on
Receive Buffer 1
Receive Buffer 0
Receive Buffer N
(In memory)
AT32UC3A
451
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