MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 118

• Manufacturer Part Number: MC908AZ60ACFU
• Description: IC MCU FLASH 8.4MHZ 60K 64QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

System Integration Module (SIM)
9.4.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. See
free-running after all reset states. See
internal reset recovery sequences.
9.5 Program Exception Control
Normal, sequential program execution can be changed in three different ways:
9.5.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume.
interrupt entry timing.
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared), see
118
•
•
•
INTERRUPT
MODULE
I BIT
R/W
IDB
IAB
Interrupts
–
–
Reset
Break interrupts
Maskable hardware CPU interrupts
Non-maskable software interrupt instruction (SWI)
DUMMY
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
DUMMY
Figure 9-10
SP
PC – 1[7:0]
SP – 1
shows interrupt recovery timing.
PC – 1[15:8]
Figure 9-8
9.3.2 Active Resets from Internal Sources
SP – 2
X
Figure
.
SP – 3
Interrupt Entry
9.6.2 Stop Mode
9-9.
A
SP – 4
CCR
VECT H
V DATA H
for details. The SIM counter is
VECT L
V DATA L
for counter control and
START ADDR
Figure 9-8
Freescale Semiconductor
OPCODE
shows