MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 129

• Manufacturer Part Number: MC908AZ60ACFU
• Description: IC MCU FLASH 8.4MHZ 60K 64QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

10.3.1 Crystal Oscillator Circuit
The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the
input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal enables the crystal oscillator
circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal
frequency. CGMXCLK is then buffered to produce CGMRCLK, the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing for operation. The duty cycle of
CGMXCLK is not guaranteed to be 50% and depends on external factors, including the crystal and related
external components.
An externally generated clock also can feed the OSC1 pin of the crystal oscillator circuit. Connect the
external clock to the OSC1 pin and let the OSC2 pin float.
10.3.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending
on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes
either automatically or manually.
Freescale Semiconductor
PLL Bandwidth Control Register (PB-
PLL Programming Register (PPG)
PLL Control Register (PCTL)
Register Name
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
WC)
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
Table 10-1. I/O Register Address Summary
Register
Address
Figure 10-2. I/O Register Summary
PLLIE
AUTO
MUL7
Bit 7
0
0
0
$001C
PCTL
= Unimplemented
LOCK
MUL6
PLLF
6
0
0
1
PLLON
MUL5
ACQ
PBWC
$001D
5
1
0
1
MUL4
BCS
XLD
4
0
0
0
$001E
PPG
VRS7
3
1
1
0
0
0
VRS6
2
1
1
0
0
1
Functional Description
VRS5
1
1
1
0
0
1
VRS4
Bit 0
1
1
0
0
0
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