MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 141

• Manufacturer Part Number: MC908AZ60ACFU
• Description: IC MCU FLASH 8.4MHZ 60K 64QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

1 MHz, the acquisition time is the time taken for the frequency to reach 1 MHz ±50 kHz. Fifty kHz = 5%
of the 1-MHz step input. If the system is operating at 1 MHz and suffers a –100 kHz noise hit, the
acquisition time is the time taken to return from 900 kHz to 1 MHz ±5 kHz. Five kHz = 5% of the 100-kHz
step input.
Other systems refer to acquisition and lock times as the time the system takes to reduce the error between
the actual output and the desired output to within specified tolerances. Therefore, the acquisition or lock
time varies according to the original error in the output. Minor errors may not even be registered. Typical
PLL applications prefer to use this definition because the system requires the output frequency to be
within a certain tolerance of the desired frequency regardless of the size of the initial error.
The discrepancy in these definitions makes it difficult to specify an acquisition or lock time for a typical
PLL. Therefore, the definitions for acquisition and lock times for this module are:
Obviously, the acquisition and lock times can vary according to how large the frequency error is and may
be shorter or longer in many cases.
10.9.2 Parametric Influences on Reaction Time
Acquisition and lock times are designed to be as short as possible while still providing the highest possible
stability. These reaction times are not constant, however. Many factors directly and indirectly affect the
acquisition time.
The most critical parameter which affects the reaction times of the PLL is the reference frequency,
f
how often the PLL makes corrections. For stability, the corrections must be small compared to the desired
frequency, so several corrections are required to reduce the frequency error. Therefore, the slower the
reference the longer it takes to make these corrections. This parameter is also under user control via the
choice of crystal frequency f
Another critical parameter is the external filter capacitor. The PLL modifies the voltage on the VCO by
adding or subtracting charge from this capacitor. Therefore, the rate at which the voltage changes for a
given frequency error (thus a change in charge) is proportional to the capacitor size. The size of the
capacitor also is related to the stability of the PLL. If the capacitor is too small, the PLL cannot make small
enough adjustments to the voltage and the system cannot lock. If the capacitor is too large, the PLL may
not be able to adjust the voltage in a reasonable time. See
Also important is the operating voltage potential applied to V
characteristics of the PLL. A fixed value is best. Variable supplies, such as batteries, are acceptable if
they vary within a known range at very slow speeds. Noise on the power supply is not acceptable,
because it causes small frequency errors which continually change the acquisition time of the PLL.
Freescale Semiconductor
CGMRDV
•
•
Acquisition time, t
frequency and the desired output frequency to less than the tracking mode entry tolerance, Δ
Acquisition time is based on an initial frequency error, (f
automatic bandwidth control mode (see
acquisition time expires when the ACQ bit becomes set in the PLL bandwidth control register
(PBWC).
Lock time, t
and the desired output frequency to less than the lock mode entry tolerance, Δ
based on an initial frequency error, (f
bandwidth control mode, lock time expires when the LOCK bit becomes set in the PLL bandwidth
control register (PBWC). (See
(please reference
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Lock
, is the time the PLL takes to reduce the error between the actual output frequency
acq
, is the time the PLL takes to reduce the error between the actual output
Figure
CGMXCLK
10-1). This frequency is the input to the phase detector and controls
.
10.3.2.3 Manual and Automatic PLL Bandwidth
des
10.3.2.3 Manual and Automatic PLL Bandwidth
– f
orig
)/f
des
, of not more than ±100%. In automatic
10.9.3 Choosing a Filter
DDA
des
. The power supply potential alters the
– f
orig
)/f
Acquisition/Lock Time Specifications
des
, of not more than ±100%. In
Capacitor.
Lock
Modes).
. Lock time is
Modes),
trk
141
.