MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 245

• Manufacturer Part Number: MC908AZ60ACFU
• Description: IC MCU FLASH 8.4MHZ 60K 64QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

If PIT functions are not required during wait mode, reduce power consumption by stopping the PIT before
executing the WAIT instruction.
21.5.2 Stop Mode
The PIT is inactive after the execution of a STOP instruction. The STOP instruction does not affect
register conditions or the state of the PIT counter. PIT operation resumes when the MCU exits stop mode
after an external interrupt.
21.6 PIT During Break Interrupts
A break interrupt stops the PIT counter.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state (see
To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a status bit is
cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state),
software can read and write I/O registers during the break state without affecting status bits. Some status
bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is at 0. After the break, doing the
second step clears the status bit.
21.7 I/O Registers
The following I/O registers control and monitor operation of the PIT:
21.7.1 PIT Status and Control Register
The PIT status and control register:
Freescale Semiconductor
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PIT status and control register (PSC)
PIT counter registers (PCNTH–PCNTL)
PIT counter modulo registers (PMODH–PMODL)
Enables PIT interrupt
Flags PIT overflows
Stops the PIT counter
Resets the PIT counter
Prescales the PIT counter clock
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
9.7.3 SIM Break Flag Control
Register).
PIT During Break Interrupts
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