MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 287

• Manufacturer Part Number: MC908AZ60ACFU
• Description: IC MCU FLASH 8.4MHZ 60K 64QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

23.13.1 MSCAN08 Module Control Register 0
SYNCH — Synchronized Status
TLNKEN — Timer Enable
SLPAK — Sleep Mode Acknowledge
SLPRQ — Sleep Request, Go to Internal Sleep Mode
SFTRES — Soft Reset
Freescale Semiconductor
This bit indicates whether the MSCAN08 is synchronized to the CAN bus and as such can participate
in the communication process.
This flag is used to establish a link between the MSCAN08 and the on-chip timer (see
This flag indicates whether the MSCAN08 is in module internal sleep mode. It shall be used as a
handshake for the sleep mode request (see
bus activity while in Sleep mode, it clears the flag.
This flag requests the MSCAN08 to go into an internal power-saving mode (see
Sleep
When this bit is set by the CPU, the MSCAN08 immediately enters the soft reset state. Any ongoing
transmission or reception is aborted and synchronization to the bus is lost.
The following registers enter and stay in their hard reset state: CMCR0, CRFLG, CRIER, CTFLG, and
CTCR.
The registers CMCR1, CBTR0, CBTR1, CIDAC, CIDAR0–3, and CIDMR0–3 can only be written by
the CPU when the MSCAN08 is in soft reset state. The values of the error counters are not affected
by soft reset.
When this bit is cleared by the CPU, the MSCAN08 tries to synchronize to the CAN bus. If the
MSCAN08 is not in bus-off state, it will be synchronized after 11 recessive bits on the bus; if the
MSCAN08 is in bus-off state, it continues to wait for 128 occurrences of 11 recessive bits.
Clearing SFTRES and writing to other bits in CMCR0 must be in separate instructions.
1 = MSCAN08 synchronized to the CAN bus
0 = MSCAN08 not synchronized to the CAN bus
1 = The MSCAN08 timer signal output is connected to the timer input.
0 = The port is connected to the timer input.
1 = Sleep – MSCAN08 in internal sleep mode
0 = Wakeup – MSCAN08 is not in Sleep mode
1 = Sleep — The MSCAN08 will go into internal sleep mode.
0 = Wakeup — The MSCAN08 will function normally.
1 = MSCAN08 in soft reset state
0 = Normal operation
Mode).
Address:
Reset:
Read:
Write:
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
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Bit 7
0
0
Figure 23-15. Module Control Register 0 (CMCR0)
= Unimplemented
6
0
0
5
0
0
23.8.1 MSCAN08 Sleep
SYNCH
4
0
TLNKEN
3
0
Programmer’s Model of Control Registers
SLPAK
2
0
Mode). If the MSCAN08 detects
SLPRQ
1
0
23.8.1 MSCAN08
SFTRES
Bit 0
1
23.9 Timer
Link).
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