MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 322

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MC908AZ60ACFU

Manufacturer Part Number
MC908AZ60ACFU
Description
IC MCU FLASH 8.4MHZ 60K 64QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908AZ60ACFU

Core Processor
HC08
Core Size
8-Bit
Speed
8.4MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
52
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 15x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Timer Interface Module A (TIMA)
ELSxB and ELSxA — Edge/Level Select Bits
322
MSxB
When ELSxB:A = 00, this read/write bit selects the initial output level of the TACHx pin once PWM,
output compare mode or input capture mode is enabled. See
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x.
When channel x is an output compare channel, ELSxB and ELSxA control the channel x output
behavior when an output compare occurs.
When ELSxB and ELSxA are both clear, channel x is not connected to port E or port F and pin
PTEx/TACHx or pin PTFx/TACHx is available as a general-purpose I/O pin. However, channel x is at
a state determined by these bits and becomes transparent to the respective pin when PWM, input
capture mode or output compare operation mode is enabled.
ELSxA work. Reset clears the ELSxB and ELSxA bits.
X
X
0
0
0
0
0
0
0
1
1
1
1 = Initial output level low
0 = Initial output level high
MSxA
X
X
X
0
1
0
0
0
1
1
1
1
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIMA status and control register (TASC).
Before enabling a TIMA channel register for input capture operation, make
sure that the PTEx/TACHx pin or PTFx/TACHx pin is stable for at least two
bus clocks.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
ELSxB
0
0
0
1
1
0
0
1
1
0
1
1
Table 25-2. Mode, Edge, and Level Selection
ELSxA
0
0
1
0
1
0
1
0
1
1
0
1
Output compare
Buffered output
buffered PWM
Output preset
Input capture
compare or
or PWM
Mode
NOTE
NOTE
Pin under port control; initial output level high
Pin under port control; initial output level low
Capture on rising edge only
Capture on falling edge only
Capture on rising or falling edge
Software compare only
Toggle output on compare
Clear output on compare
Set output on compare
Toggle output on compare
Clear output on compare
Set output on compare
Table 25-2
Table
25-2. Reset clears the MSxA bit.
Configuration
shows how ELSxB and
Freescale Semiconductor

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