MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 323

• Manufacturer Part Number: MC908AZ60ACFU
• Description: IC MCU FLASH 8.4MHZ 60K 64QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TOVx — Toggle-On-Overflow Bit
CHxMAX — Channel x Maximum Duty Cycle Bit
25.8.5 TIMA Channel Registers
These read/write registers contain the captured TIMA counter value of the input capture function or the
output compare value of the output compare function. The state of the TIMA channel registers after reset
is unknown.
In input capture mode (MSxB–MSxA = 0:0) reading the high byte of the TIMA channel x registers
(TACHxH) inhibits input captures until the low byte (TACHxL) is read.
In output compare mode (MSxB–MSxA ≠ 0:0) writing to the high byte of the TIMA channel x registers
(TACHxH) inhibits output compares and the CHxF bit until the low byte (TACHxL) is written.
Freescale Semiconductor
When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the TIMA counter overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
When the TOVx bit is at logic 1, setting the CHxMAX bit forces the duty cycle of buffered and
unbuffered PWM signals to 100%. As
it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is
cleared.
1 = Channel x pin toggles on TIMA counter overflow.
0 = Channel x pin does not toggle on TIMA counter overflow.
Figure 25-9. TIMA Channel Registers (TACH0H/L–TACH5H/L) (Sheet 1 of 3)
Register Name and Address
PTEx/TCHx
When TOVx is set, a TIMA counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX
Reset:
Read:
Write:
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
OVERFLOW
Bit 15
Bit 7
COMPARE
PERIOD
OUTPUT
Bit 14
6
Figure 25-8. CHxMAX Latency
OVERFLOW
TACH0H — $0027
Figure 25-8
Bit 13
5
COMPARE
OUTPUT
Indeterminate after Reset
NOTE
Bit 12
OVERFLOW
4
shows, the CHxMAX bit takes effect in the cycle after
Bit 11
COMPARE
OUTPUT
3
OVERFLOW
Bit 10
2
COMPARE
OUTPUT
Bit 9
1
OVERFLOW
Bit 0
Bit 8
I/O Registers
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