MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 337

• Manufacturer Part Number: MC908AZ60ACFU
• Description: IC MCU FLASH 8.4MHZ 60K 64QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

27.3.1 BDLC Operating Modes
The BDLC has five main modes of operation which interact with the power supplies, pins, and the
remainder of the MCU as shown in
27.3.1.1 Power Off Mode
This mode is entered from reset mode whenever the BDLC supply voltage, V
specified value for the BDLC to guarantee operation. The BDLC will be placed in reset mode by
low-voltage reset (LVR) before being powered down. In this mode, the pin input and output specifications
are not guaranteed.
27.3.1.2 Reset Mode
This mode is entered from the power off mode whenever the BDLC supply voltage, V
minimum specified value (V
must be asserted while powering up the BDLC or an unknown state will be entered and correct operation
cannot be guaranteed. Reset mode is also entered from any other mode as soon as one of the MCU’s
possible reset sources (such as LVR, POR, COP watchdog, and reset pin, etc.) is asserted.
In reset mode, the internal BDLC voltage references are operative; V
which are held in their reset state; and the internal BDLC system clock is running. Registers will assume
their reset condition. Outputs are held in their programmed reset state. Therefore, inputs and network
activity are ignored.
Freescale Semiconductor
NETWORK ACTIVITY OR
OTHER MCU WAKEUP
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
BDLC STOP
Figure 27-3. BDLC Operating Modes State Diagram
ANY MCU RESET SOURCE ASSERTED
COP, ILLADDR, PU, RESET, LVR, POR
DD
V
DD
STOP INSTRUCTION OR
WAIT INSTRUCTION AND WCM = 1
–10%) and some MCU reset source is asserted. The internal MCU reset
≤ V
(FROM ANY MODE)
DD
(MINIMUM)
Figure
27-3.
POWER OFF
RESET
RUN
V
ANY MCU RESET SOURCE ASSERTED
DD
> V
NO MCU RESET SOURCE ASSERTED
DD
WAIT INSTRUCTION AND WCM = 0
(MINIMUM) AND
DD
is supplied to the internal circuits
NETWORK ACTIVITY OR
OTHER MCU WAKEUP
BDLC WAIT
DD
, drops below its minimum
Functional Description
DD
, rises above its
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