MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 340

• Manufacturer Part Number: MC908AZ60ACFU
• Description: IC MCU FLASH 8.4MHZ 60K 64QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Byte Data Link Controller (BDLC)
The counter will increment if the input data sample is high but decrement if the input sample is low.
Therefore, the counter will thus progress either up toward 15 if, on average, the BDRxD signal remains
high or progress down toward 0 if, on average, the BDRxD signal remains low.
When the counter eventually reaches the value 15, the digital filter decides that the condition of the
BDRxD signal is at a stable logic level 1 and the data latch is set, causing the filtered Rx data signal to
become a logic level 1. Furthermore, the counter is prevented from overflowing and can only be
decremented from this state.
Alternatively, should the counter eventually reach the value 0, the digital filter decides that the condition
of the BDRxD signal is at a stable logic level 0 and the data latch is reset, causing the filtered Rx data
signal to become a logic level 0. Furthermore, the counter is prevented from underflowing and can only
be incremented from this state.
The data latch will retain its value until the counter next reaches the opposite end point, signifying a
definite transition of the signal.
27.4.1.2 Performance
The performance of the digital filter is best described in the time domain rather than the frequency domain.
If the signal on the BDRxD signal transitions, then there will be a delay before that transition appears at
the filtered Rx data output signal. This delay will be between 15 and 16 clock periods, depending on where
the transition occurs with respect to the sampling points. This filter delay must be taken into account when
performing message arbitration.
For example, if the frequency of the MUX interface clock (f
) is 1.0486 MHz, then the period (t
)
BDLC
BDLC
is 954 ns and the maximum filter delay in the absence of noise will be 15.259 μs.
The effect of random noise on the BDRxD signal depends on the characteristics of the noise itself. Narrow
noise pulses on the BDRxD signal will be ignored completely if they are shorter than the filter delay. This
provides a degree of low pass filtering.
If noise occurs during a symbol transition, the detection of that transition can be delayed by an amount
equal to the length of the noise burst. This is just a reflection of the uncertainty of where the transition is
truly occurring within the noise.
Noise pulses that are wider than the filter delay, but narrower than the shortest allowable symbol length,
will be detected by the next stage of the BDLC’s receiver as an invalid symbol.
Noise pulses that are longer than the shortest allowable symbol length will be detected normally as an
invalid symbol or as invalid data when the frame’s CRC is checked.
27.4.2 J1850 Frame Format
All messages transmitted on the J1850 bus are structured using the format shown in .
J1850 states that each message has a maximum length of 101 PWM bit times or 12 VPW bytes, excluding
SOF, EOD, NB, and EOF, with each byte transmitted MSB first.
All VPW symbol lengths in the following descriptions are typical values at a 10.4 kbps bit rate.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
340
Freescale Semiconductor